Interrupt Pending Register; Table 9-7 Interrupt Pending Register Description - Motorola MC68VZ328 User Manual

Programming Model
9.6.5

Interrupt Pending Register

The read-only interrupt pending register (IPR) indicates which interrupts are pending. If an interrupt
source requests an interrupt, but that interrupt is masked by the interrupt mask register, then that interrupt
bit will be set in this register, but not in the interrupt status register. If the pending interrupt is not masked,
the interrupt bit will be set in both registers.
IPR
BIT
30
31
TYPE
RESET 0 0
BIT
14
15
PW
M2
TYPE
0 0
RESET
Name
Reserved Reserved
Bits 31–24
EMIQ Emulator Interrupt Pending—When set, this bit indicates that the
Bit 23 in-circuit emulation module or EMUIRQ pin is requesting an interrupt
on level 7. This bit can be generated from three interrupt sources:
two breakpoint interrupts from the in-circuit emulation module and an
external interrupt from EMUIRQ, which is an active low, edge-sensi-
tive interrupt. To clear this interrupt, you must read the ICEMSR reg-
ister to identify the interrupt source and write a 1 to the
corresponding bit of that register. See Section 16.2.4, "In-Circuit
Emulation Module Status Register," on page 16-10 for more informa-
tion.
RTI Real-Time Interrupt Pending (Real-Time Clock)—When set, this
Bit 22 bit indicates that the real-time timer interrupt is pending. The fre-
quency can be selected inside the real-time clock module, which can
function as an additional timer.
SPI1 SPI 1 Interrupt Pending—When set, this bit indicates an interrupt
Bit 21 event from SPI unit 1.
9-16
Interrupt Pending Register
29 28 27 26 25
0 0 0 0
13 12 11 10
UA
INT INT INT
RT
3 2
2
rw rw rw rw rw
0 0 0 0
Table 9-7. Interrupt Pending Register Description
Description
MC68VZ328 User's Manual
24 23 22 21
EMI SPI
RTI
Q 1
rw rw rw
0 0 0 0 0
0x00000000
9 8 7 6 5
INT PW TM
KB
1 0 M1 R2
rw rw rw rw
0 0 0 0 0
0x00000000
0x(FF)FFF310
20 19 18 17
IRQ IRQ IRQ IRQ IRQ
5 6 3 2
rw rw rw rw
0 0 0 0
4 3 2 1
UA
RT WD TM
RT
C T R1
1
rw rw rw rw
0 0 0 0
Settings
These bits are reserved and
should be set to 0.
0 = No emulator interrupt is
pending.
1 = An emulator interrupt is
pending.
0 = No real-time timer
interrupt is pending.
1 = A real-time timer interrupt
is pending.
0 = No SPI 1 interrupt is
pending.
1 = An SPI 1 interrupt is
pending.
BIT
16
1
rw
0
BIT
0
SPI
2
rw
0