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Table 8-15. LCD Refresh Rate Adjustment Register Description (Continued)
Name
RRAx
Refresh Rate 9–0—These bits contain the frame period, which can be calculated as
Bits 9–0
follows:
FRAME PERIOD = (12 + XMAX + RRA) x YMAX x (PXCD + 1) x LCDCLK_PERIOD
where:
Frame period = time for each screen update
XMAX = screen width in number of pixels
RRA = hexadecimal value stored in the LRRA register
YMAX = screen height in number of pixels
PXCD = hexadecimal value stored in the LPXCD register
LCDCLK_PERIOD: refer to Section 4.4.1, "PLL Control Register," on page 4-8 for
setting LCDCLK period
8.3.15
LCD Panning Offset Register
The LCD panning offset register (LPOSR) is used to control how many pixels the picture is shifted to the
.
left
The bit assignments for the register are shown in the following register display. The settings for the
bits in the register are listed in Table 8-16.
LPOSR
BIT 7
TYPE
0
RESET
Name
Reserved
Reserved
–
Bits 7
4
POSx
Pixel Offset Code—These bits specify the number
–0
Bits 3
of pixels being shifted to the left of the display panel.
This is independent of the black-and-white or gray
mode.
Note:
When the LOPSR register is being modified, the software must adjust the cursor's reference position.
8.3.16
LCD Frame Rate Control Modulation Register
This register of address space 0x(FF)FFFA31 is used for frame rate modulation control in the
MC68EZ328, but it is unused in the MC68VZ328. This register is removed and not available for the
temporary storage of data.
Description
LCD Panning Offset Register
6
5
0
0
Table 8-16. LCD Panning Offset Register Description
Description
LCD Controller
4
3
2
POS3
POS2
rw
rw
0
0
0
0x00
These bits are reserved and should be set to
0.
0001 = Picture is shifted 1 pixel to the left.
0010 = Picture is shifted 2 pixels to the left.
.
.
.
1111 = Picture is shifted 15 pixels to the left.
Programming Model
Setting
See descrip-
tion.
0x(FF)FFFA2D
1
BIT 0
POS1
POS0
rw
rw
0
0
Setting
8-19
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