In-Circuit Emulation Module Control Register; Table 16-4 Ice Module Control Register Description - Motorola MC68VZ328 User Manual

Programming Model
16.2.3

In-Circuit Emulation Module Control Register

The in-circuit emulation module control register (ICEMCR) is used to control the in-circuit emulation
module. The bit assignments for the ICE module control register are shown in the following register
display. The settings for the bits are described in Table 16-4.
ICEMCR
BIT 15 14
TYPE
0 0
RESET
Name
Reserved Reserved
Bits 15–7
SWEN Software Enable EMU Module—In normal mode, writing to
Bit 6 this bit enables the breakpoint function.
Reserved Reserved
Bit 5
BBIEN Bus Break Interrupt Enable—When set, this bit enables the
Bit 4 generation of a level 7 interrupt on a bus breakpoint.
HMDIS Hard-Map Disable—In emulation mode, this bit activates the
Bit 3 internal hard-map operation. When this bit is clear, some
memory locations are hard-coded to the specific values
shown in Table 16-5 on page 16-9. If this bit is set or in nor-
mal mode, memory reads to these locations refer to the exter-
nal memory.
Note: It is important to note that when writing to these
locations, all writes are occurring to external memory. When
the HMDIS bit is disabled, reads to these addresses are in
word or long-word sizes.
SB Single BreakPoint—This bit controls the direction of the
Bit 2 EMUBRK signal. In multiple breakpoint mode, the external
address comparator will compare the lower address bits and
the internal comparator will compare the higher address bits
to generate a breakpoint matched signal.
PBEN Program Break Enable—This bit is used to select a program
Bit 1 or bus break.
16-8
ICE Module Control Register
13 12 11 10 9 8
0 0 0 0 0 0
Table 16-4. ICE Module Control Register Description
Description
MC68VZ328 User's Manual
7 6 5 4
SWEN BBIEN
rw rw
0 0 0 0
0x0000
These bits are reserved and should
be set to 0.
0 = Disable breakpoint function.
1 = Enable breakpoint function.
This bit is reserved and should be
set to 0.
0 = Disable level 7 interrupt
1 = Enable level 7 interrupt
See Table 16-5 on page 16-9.
0 = Configure the EMUBRK signal as
1 = Configure the EMUBRK signal as
0 = Select a bus break.
1 = Select a program break.
0x(FF)FFFFFD0C
3 2 1 BIT 0
HMDIS SB PBEN CEN
rw rw rw
0 0 0
Setting
generation on a bus breakpoint.
generation on a bus breakpoint.
an input (multiple breakpoint
mode with external address
compare for the lower
addresses).
an output (single breakpoint
based on the internal address
compare register).
rw
0