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Programming Model
10.4.8
Port G Registers
Port G is comprised of the following 8-bit general-purpose I/O registers:
•
Port G direction register (PGDIR)
•
Port G data register (PGDATA)
•
Port G pull-up enable register (PGPUEN)
•
Port G select register (PGSEL)
Each signal in the PGDATA register connects to an external pin. It should be noted that pins 6 and 7 are
not connected to external pins. Port G provides a total of six pins, and each bit is individually configured.
10.4.8.1
Port G Direction Register
The Port G direction register controls the direction (input or output) of the line associated with the
PGDATA bit position. When the data bit is assigned to a dedicated I/O function by the PGSEL register, the
DIR bits are ignored. The settings for the PGDIR bit positions are shown in Table 10-36.
PGDIR
BIT 7
TYPE
0
RESET
Name
Reserved
Reserved
Bits 7–6
DIRx
Direction—These bits control the direction of
Bits 5–0
the pins in an 8-bit system. They reset to 0.
10.4.8.2
Port G Data Register
The settings for the bit positions of the PGDATA register are shown in Table 10-37 on page 10-29.
10-28
Port G Direction Register
6
5
DIR5
rw
0
0
Table 10-36. Port G Direction Register Description
Description
MC68VZ328 User's Manual
4
3
2
DIR4
DIR3
DIR2
rw
rw
rw
0
0
0
0x00
These bits are reserved and should be set to
0.
0 = Input
1 = Output
0x(FF)FFF430
1
BIT 0
DIR1
DIR0
rw
rw
0
0
Setting
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