Programming Model; Timer Control Registers 1 And 2; Table 12-2 Timer Control Register Description - Motorola MC68VZ328 User Manual

Programming Model

12.2 Programming Model
The following sections provide programming information about the settings of the two 16-bit timers in the
GP timers module. Because the two timers are identical, the register description and the associated table
describing the register settings apply to both registers.
12.2.1

Timer Control Registers 1 and 2

Each timer control (TCTLx) register controls the overall operation of its corresponding GP timer. The
settings for the registers are described in Table 12-2. The TCTL registers control the following:
• Selecting the free-running or restart mode after a compare event
• Selecting the capture trigger event
• Controlling the output compare mode
• Enabling the compare event interrupt
• Selecting the prescaler clock source
• Enabling and disabling the GP Timer
TCTL1
BIT
14
15
TYPE
0 0
RESET
TCTL2
BIT
14
15
TYPE
0 0
RESET
Name
Reserved Reserved
Bits 15–9
FRR Free-Running/Restart—This bit controls the
Bit 8 counter mode of operation after a compare
event occurs. In free-running mode, the
counter continues after the compare. In restart
mode, the counter resets to 0x0000 and
resumes counting.
12-6
Timer Control Register 1
13 12 11 10
0 0 0 0
Timer Control Register 2
13 12 11 10
0 0 0 0
Table 12-2. Timer Control Register Description
Description
MC68VZ328 User's Manual
9 8 7 6 5
FRR CAP OM
rw rw rw rw
0 0 0 0 0
0x0000
9 8 7 6 5
FRR CAP OM
rw rw rw rw
0 0 0 0 0
0x0000
These bits are reserved and should be set to 0.
0 = Restart mode (default).
1 = Free-running mode.
0x(FF)FFF600
4 3 2 1
IRQEN CLKSOURCE TEN
rw rw rw rw
0 0 0 0
0x(FF)FFF610
4 3 2 1
IRQEN CLKSOURCE TEN
rw rw rw rw
0 0 0 0
Setting
BIT
0
rw
0
BIT
0
rw
0