Fifo Level Marker Interrupt Register; Table 14-16 Fifo Level Marker Interrupt Register Description - Motorola MC68VZ328 User Manual

14.4.14

FIFO Level Marker Interrupt Register

The UART FIFO level marker register configures the level at which either the RxFIFO or the TxFIFO
reports a half-full condition. The bit position assignments for this register are shown in the following
register display. The settings for this register are described in Table 14-16.
HMARK
BIT 15 14
TYPE
0 0
RESET
Table 14-16. FIFO Level Marker Interrupt Register Description
Name
Reserved Reserved
Bits 15–12
TXFIFO TxFIFO Level Marker—This field defines the level at which
LEVEL the TxFIFO marker is set. When the TxFIFO status matches
MARKER the level marker selected here, the TxFIFO half status bit is set
Bits 11–8 and the TXFIFO HALF interrupt is generated if it is enabled.
Reserved Reserved
Bits 7–4
RXFIFO RxFIFO Level Marker—This field defines the level at which
LEVEL the RxFIFO marker is set. When the RxFIFO status matches
MARKER the level marker selected here, the RxFIFO half status bit is
Bits 3–0 set and the RXFIFO HALF interrupt is generated if it is
enabled.
Universal Asynchronous Receiver/Transmitter 1 and 2
FIFO Level Marker Interrupt Register
13 12 11 10
TXFIFO LEVEL MARKER
rw rw
0 0 0 0
Description
9 8 7 6 5
rw rw
0 1 0 0 0
0x0102
These bits are reserved and should
be set to 0.
See Table 14-17 on page 14-30 for
settings.
These bits are reserved and should
be set to 0.
See Table 14-17 on page 14-30 for
settings.
Programming Model
0x(FF)FFF91C
4 3 2 1 BIT 0
RXFIFO LEVEL MARKER
rw rw rw rw
0 0 0 1 0
Setting
14-29