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10.4.5.5
Port D Select Register
The Port D select register (PDSEL) determines if a bit position in the Port D data register (PDDATA) is
assigned as a GPIO or to a dedicated I/O function. The settings for the bit positions of PDSEL are shown in
Table 10-21.
PDSEL
BIT 7
SEL7
TYPE
RESET
Name
SELx
Select—These bits select whether the internal
Bits 7–4
chip function or I/O port signals are connected to
the pins.
Reserved
Reserved
Bits 3–0
10.4.5.6
Port D Polarity Register
These bits select the input signal polarity of INT[3:0]. The polarity of the rising or falling edge is selected
by the POLx bits. Interrupts are active high (or rising edge) when these bits are low. Interrupts are active
low (or falling edge) while these bits are high. The settings for the bit positions of PDPOL are shown in
Table 10-22.
PDPOL
BIT 7
TYPE
RESET
Name
Reserved
Reserved
Bits 7–4
POLx
Polarity—These bits determine the input signal
Bits 3–0
polarity of INT[3:0] interrupts.
Port D Select Register
6
5
SEL6
SEL5
rw
rw
rw
1
1
1
Table 10-21. Port D Select Register Description
Description
Port D Polarity Register
6
5
0
0
0
Table 10-22. Port D Polarity Register Description
Description
I/O Ports
4
3
2
SEL4
rw
1
0
0
0xF0
0 = The dedicated function pins are connected.
1 = The I/O port function pins are connected.
These bits are reserved and should be set to 0.
4
3
2
POL3
POL2
rw
rw
0
0
0
0x00
These bits are reserved and should be set to 0.
0 = Data is unchanged.
1 = The input data is inverted before being
presented to the holding register.
Programming Model
0x(FF)FFF41B
1
BIT 0
0
0
Setting
0x(FF)FFF41C
1
BIT 0
POL1
POL0
rw
rw
0
0
Setting
10-19
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