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Programming Model
14.4.5
UART 1 Miscellaneous Register
The UART 1 miscellaneous (UMISC1) register contains miscellaneous bits to control test features of the
UART 1 module. Some bits, however, are only used for factory testing and should not be used. The bit
position assignments for this register are shown in the following register display. The settings for this
register are described in Table 14-8.
UMISC1
BIT
14
15
BA
UD
CLK
TES
SRC
T
TYPE
rw
rw
0
0
RESET
Table 14-8. UART 1 Miscellaneous Register Description
Name
BAUD
Baud Rate Generator Testing—This bit puts the baud rate
TEST
generator in test mode. The integer and non-integer prescal-
Bit 15
ers, as well as the divider, are broken into 4-bit nibbles for test-
ing. This bit should remain 0 for normal operation.
CLKSRC
Clock Source—This bit selects the source of the 1x bit clock
Bit 14
for transmission and reception. When this bit is high, the bit
clock is derived directly from the UCLK pin (it must be config-
ured as an input). When it is low (normal), the bit clock is sup-
plied by the baud rate generator. This bit allows high-speed
synchronous applications, in which a clock is provided by the
external system.
FORCE
Force Parity Error—When this bit is high, it forces the trans-
PERR
mitter to generate parity errors, if parity is enabled. This bit is
Bit 13
for system debugging.
LOOP
Loopback—This bit controls loopback for system testing pur-
Bit 12
poses. When this bit is high, the receiver input is internally con-
nected to the transmitter and ignores the RXD1 pin. The TXD1
pin is unaffected by this bit.
BAUD
Baud Rate Generator Reset—This bit resets the baud rate
RESET
generator counters.
Bit 11
IRTEST
Infrared Testing—This bit connects the output of the IrDA cir-
Bit 10
cuitry to the TXD1 pin. This provides test visibility to the IrDA
module.
Reserved
Reserved
Bits 9–8
14-16
UART 1 Miscellaneous Register
13
12
11
FORCE
LO
BAUD
PERR
OP
RESET
rw
rw
rw
0
0
0
Description
MC68VZ328 User's Manual
10
9 8
7
6
RT
IR
S1
RT
TES
CO
S1
T
NT
rw
rw
rw
0
0 0
0
0
0x0000
0 = Normal mode.
1 = Test mode.
0 = Bit clock is generated by the
1 = Bit clock is supplied by the
0 = Generate normal parity.
1 = Generate inverted parity (error).
0 = Normal receiver operation.
1 = Internally connects the
0 = Normal operation.
1 = Reset baud counters.
0 = Normal operation.
1 = IrDA test mode.
These bits are reserved and should
be set to 0.
0x(FF)FFF908
5
4
3
2
1
IRD
R
TX
IRD
A
X
P
AEN
LO
P
OL
OP
OL
rw
rw
rw
rw
0
0
0
0
0
Setting
baud rate generator.
UCLK pin.
transmitter output to the
receiver input.
BIT
0
0
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