Dma Control Register; Table 8-20 Dma Control Register Description; Programming Example - Motorola MC68VZ328 User Manual

Programming Example

8.3.20

DMA Control Register

The LCD controller contains an 8
data is then passed to the LCD for display. When enough data has been removed from the buffer that it
needs to be refilled, a new DMA transfer must be initiated. The DMA control register controls when the
buffer should be refilled and the DMA burst length used when refilling. The bit assignments for the
register are shown in the following register display. The settings for the bits are listed in Table 8-20.
DMACR
BIT 7
TYPE rw
0
RESET
Name
DMABL[3:0] DMA Burst Length—This field sets the number of words to be
–
Bits 7 4 loaded to the pixel buffer in each DMA cycle.
Reserved Reserved
Bit 3
DMATM[2:0] DMA Trigger Mark—This field sets the low-level mark in the pixel
–
Bits 2 0 buffer to trigger a DMA request. The low-level mark equals to the
number of words left in the pixel buffer.
Note: Since the FIFO size is 8
F_HI + F_LO <= 8
1 <= F_HI <= 8
1<= F_LO <= 6
8.4 Programming Example
The following is an example of how to program the related registers to properly configure an LCD panel
with a resolution of 240
image is 320 pixels wide and panned by 3 pixels.
LCDINT move.l #$A80000,#$FFFA00
move.w #240,#$FFFA08
move.w #159,#$FFFA0A
move.b #40,#$FFFA05
move.b #$09,#$FFFA20
move.b #3,#$FFFA25
move.b #10,#$FFFA29
move.b #$03,#$FFFA2D
move.b #$82,#$FFFA27
8-22
×
16 pixel buffer, which stores DMA-in data from system memory. This
DMA Control Register
6 5
DMABL[3:0]
rw rw
1 1
Table 8-20. DMA Control Register Description
Description
×
16, DMABL and DMATM must be programmed based on the following criteria:
×
160 pixels, 4 levels of grayscale, and a 4-bit LCD data interface. The virtual
Example 8-1. Programming Example
MC68VZ328 User's Manual
4 3
rw
0 0
0x62
;display data address starts at $A80000
;LCD horizontal size is 240
;LCD vertical size is 160
;4 level gray and 320 pixels wide image
;LCD panel data bus is 4 bits,4 level gray
;pixel clock rate equal 1/4 of LCDCLK from PLL
;refresh rate adjustment
;shift picture by 3 pixels
;switch on LCDC, 2 wait state for memory cycle
0x(FF)FFFA39
2 1 BIT 0
DMATM[2:0]
rw rw rw
0 1 0
Setting
See description and table
footnote.
This bit is reserved and
should be set to 0.
See description and table
footnote.