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LACDRC
BIT 7
ACDSLT
TYPE
rw
0
RESET
Name
ACDSLT
Clock Source Select—This bit selects the clock source for the
Bit 7
internal counter that generates an LACD signal.
ACDx
Alternate Crystal Direction Control 6–0—These bits represent
Bits 6–0
the ACD toggle rate control code. The LACD signal will toggle
once every 1 to 128 FLM/LP cycles based on the value specified
in this register. The actual number of FLM cycles is the value pro-
grammed plus one. Shorter cycles tend to give better results.
8.3.12
LCD Pixel Clock Divider Register
The LCD pixel clock divider (LPXCD) register is used to program the divider, which generates the pixel
clock. The bit assignments for the register are shown in the following register display. The settings for the
bits in the register are listed in Table 8-13.
LPXCD
BIT 7
TYPE
0
RESET
Table 8-13. LCD Pixel Clock Divider Register Description
Name
Reserved
Reserved
Bits 7–6
PCDx
Pixel Clock Divider 5–0—These bits represent the pixel clock divisor.
Bits 5–0
The LCDCLK signal from the PLL is divided by N (PCD5–0 + 1) to yield
the actual pixel clock. Values of 1–63 will yield N = 2 to N = 64. If these
bits are set to 0 (N = 1), the PIX clock will be used directly, bypassing
the divider circuit. Refer to Chapter 4, "Clock Generation Module and
Power Control Module," for more information.
LACD Rate Control Register
6
5
ACD6
ACD5
rw
rw
0
0
Table 8-12. LACD Rate Control Register Description
Description
LCD Pixel Clock Divider Register
6
5
PCD5
rw
0
0
Description
LCD Controller
4
3
2
ACD4
ACD3
ACD2
rw
rw
rw
0
0
0
0x00
0 = Select frame pulse as input
1 = Select line pulse as input
See description
4
3
2
PCD4
PCD3
PCD2
rw
rw
rw
0
0
0
0x00
Programming Model
0x(FF)FFFA23
1
BIT 0
ACD1
ACD0
rw
rw
0
0
Setting
clock
clock
0x(FF)FFFA25
1
BIT 0
PCD1
PCD0
rw
rw
0
0
Setting
These bits are reserved
and should be set to 0.
See description.
8-17
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