Interrupt Level Register; Table 9-8 Interrupt Level Register Field Values - Motorola MC68VZ328 User Manual

Motorola mc68vz328 integrated processor user's manual
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9.6.6

Interrupt Level Register

TIMER 2, UART 2, PWM 2, and SPI 1 are new modules to the MC68VZ328 compared to the previous
version, MC68EZ328. Interrupts generated from these modules are level configurable. The interrupt level
control register (ILCR) controls the interrupt level for these interrupts.
ILCR
BIT
14
15
SPI1_LEVEL
TYPE
rw
0
1
RESET
Programming register bits 14–12, 10–8, 6–4, and 2–0 with the values shown in Table 9-8 causes the
corresponding interrupt source to generate different interrupt levels.
Note: Values 000 and 111 are not allowed to be programmed into
these register bits.
After reset, each of these four interrupts is set to the default level indicated:
TIMER2IRQ (level 3)
UART2IRQ (level 5)
PWM2IRQ (level 3)
SPI2IRQ (level 6)
Interrupt Level Register
13
12
11
10
UART2_LEVEL
rw
rw
rw
rw
1
0
0
1
Table 9-8. Interrupt Level Register Field Values
Interrupt Level
Undefined level
Level 6
Level 5
Level 4
Level 3
Level 2
Level 1
Undefined level
Interrupt Controller
9
8
7
6
5
PWM2_LEVEL
rw
rw
rw
0
1
0
0
1
0x6533
Value in Register Bits
14–12, 10–8, 6–4, and 2–0
111
110
101
100
011
010
001
000
Programming Model
0x(FF)FFF314
BIT
4
3
2
1
TMR2_LEVEL
rw
rw
rw
rw
1
0
0
1
9-19
0
1

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