Status Register (Sr) Instruction Execution Times; Moves Execution Times; Miscellaneous Instruction Execution Times - Motorola M68060 User Manual

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Table 10-22. Status Register (SR) Instruction Execution Times
1
For these instructions, add the effective address calculation time.
MOVES Function
Source<SFC> -> Rn
Byte, Word 1(1/0) 1(1/0) 1(1/0)
"
Rn -> Dest <DFC>
Byte, Word 1(0/1) 1(0/1) 1(0/1)
"
1
Add 2(1/0) cycles to the (bd,An,Xi*SF) time for a memory indirect address.
Table 10-24. Miscellaneous Instruction Execution Times
Instruction
ANDI to CCR
CHK
"
CINVA
CINVL
CINVP
CPUSHA
CPUSHL
CPUSHP
EORI to CCR
EXG
EXT
"
EXTB
LINK
"
LPSTOP
MOVE from CCR
MOVE to CCR
MOVE from USP
MOVE to USP
MOVEC (SFC,DFC,
USP,VBR,PCR)
MOVEC (CACR,TC,
TTR,BUSCR,URP,SRP)
NOP
ORI to CCR
PACK
MOTOROLA
Instruction
ANDI to SR
EORI to SR
MOVE from SR
MOVE to SR
ORI to SR
Table 10-23. MOVES Execution Times
Size
(An) (An)+ –(An) (d16,An)
Long
1(1/0) 1(1/0) 1(1/0)
Long
1(0/1) 1(0/1) 1(0/1)
Size
Register
Byte
1(0/0)
Word
2(0/0)
Long
2(0/0)
Byte
1(0/0)
Long
1(0/0)
Word
1(0/0)
Long
1(0/0)
Long
1(0/0)
Word
2(0/1)
Long
2(0/1)
Word
15(0/1)
Word
1(0/0)
Word
1(0/0)
Long
1(0/0)
Long
2(0/0)
Long
Long
9(0/0)
Byte
1(0/0)
2(0/0)
M68060 USER'S MANUAL
Instruction Execution Timing
Execution Time
12(0/0)
12(0/0)
1
1(0/1)
1
12(1/0)
5(0/0)
Destination
(d8,An,Xi∗SF)
1(1/0)
2(1/0)
1(1/0)
2(1/0)
1(0/1)
2(0/1)
1(0/1)
2(0/1)
Memory
Reg -> Dest
1
2(1/0)
1
2(1/0)
<=17(0/0)
<=18(0/0)
<=274(0/0)
2
<=5394(0/512)
2
<=26(0/1)
2
<=2838(0/256)
1
1(0/1)
1
1(1/0)
12(0/0)
15(0/0)
2(1/1)
1
(bd,An,Xi∗SF)
(xxx).WL
3(1/0)
2(1/0)
3(1/0)
2(1/0)
3(0/1)
2(0/1)
3(0/1)
2(0/1)
Source -> Reg
11(0/0)
14(0/0)
10-23

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