Motorola CPU32 Manuals

Manuals and User Guides for Motorola CPU32. We have 2 Motorola CPU32 manuals available for free PDF download: Reference Manual

Motorola CPU32 Reference Manual

Motorola CPU32 Reference Manual (330 pages)

Brand: Motorola | Category: Processor | Size: 4.07 MB

Table of Contents

Table of Contents
3
Table Title Page
12
Features
15
Loop Mode Instruction Execution
16
Virtual Memory
16
Exception Handling
17
Vector Base Register
17
Enhanced Addressing Modes
18
Instruction Set
18
- Instruction Set Summary
  19
Block Diagram
20
Low-Power Stop Instruction
20
Privilege States
20
Processing States
20
CPU32 Block Diagram
21
Architecture Summary

23
- Programming Model
  23
- Registers
  24
- Data Types
  25
- Data Registers
  26
- Organization in Registers
  26
- Address Registers
  27
- Control Registers
  27
- Organization in Memory
  28
- Memory Operand Addressing
  29
Data Organization and Addressing Capabilities

31
Instruction Set

49
- Low-Power Stop (LPSTOP)
  49
- M68000 Family Compatibility
  49
- New Instructions
  49
- Instruction Format
  50
  - Table Lookup and Interpolation (TBL)
    50
- Unimplemented Instructions
  50
- Notation
  51
- Condition Code Register
  53
  - Condition Code Computations
    53
- Instruction Summary
  53
- Data Movement Instructions
  54
- Integer Arithmetic Operations
  55
- Logic Instructions
  56
- Shift and Rotate Instructions
  57
  - Shift and Rotate Operations
    57
- Binary-Coded Decimal (BCD) Instructions
  58
- Bit Manipulation Instructions
  58
- Program Control Instructions
  58
- System Control Instructions
  59
  - Condition Tests
    60
  - Condition Tests
    61
- Instruction Details
  61
- Instruction Description Format
  62
- Instruction Format Summary
  218
- State Transitions
  243
  - Supervisor Privilege Level
    244
  - Address Spaces
    245
- Types of Address Space
  245
  - Type 0000 — Breakpoint
    246
  - Type 1111 — Interrupt Acknowledge
    247
- Definition of Exception Processing
  249
  - Exception Vector Assignments
    250
  - Types of Exceptions
    250
  - Exception Processing Sequence
    251
  - Multiple Exceptions
    252
- Processing of Specific Exceptions
  253
  - Bus Error
    254
  - Address Error
    255
  - Instruction Traps
    256
  - Format Error
    257
  - Privilege Violations
    258
  - Tracing
    259
  - Interrupts
    260
  - Return from Exception
    261
- Fault Recovery
  262
  - Types of Faults
    264
    
    Type II: Prefetch, Operand, RMW, and MOVEP Faults
    265
    
    Type IV: Faults During Exception Processing
    266
    
    Type I) Completing Released Writes Via Software
    267
    
    Type III) Correcting Faults Via Software
    268
    
    Type III) Correcting Faults Via RTE
    269
  - Normal Four-Word Stack Frame
    270
- Internal Transfer Count Register
  271
- Format $C — BERR Stack for Prefetches and Operands
  272
- CPU32 Integrated Development Support
  273
  - Deterministic Opcode Tracking Overview
    274
  - On-Chip Hardware Breakpoint Overview
    275
  - Enabling BDM
    276
    
    Double Bus Fault
    277
  - Background Mode Registers
    278
    
    Current Instruction Program Counter (PCC)
    279
    
    CPU Serial Logic
    280
- Serial Interface Timing Diagram
  281
  - Development System Serial Logic
    282
  - Command Set
    283
    
    Command Sequence Diagram
    284
- Command-Sequence-Diagram Example
  285
  - Command Set Summary
    286
  - Read A/D Register (RAREG/RDREG)
    287
  - Read System Register (RSREG)
    288
  - Read Memory Location (READ)
    289
  - Write Memory Location (WRITE)
    290
  - Dump Memory Block (DUMP)
    291
  - Fill Memory Block (FILL)
    293
  - Resume Execution (GO)
    294
  - Reset Peripherals (RST)
    296
  - Future Commands
    297
- Functional Model of Instruction Pipeline
  298
  - Opcode Tracking During Loop Mode
    299
- Resource Scheduling
  301
- Instruction Pipeline
  302
  - Prefetch Controller
    303
  - Instruction Execution Overlap
    304
  - Effects of Wait States
    305
  - Effects of Negative Tails
    306
- Instruction Stream Timing Examples
  307
  - Timing Example 2: Branch Instructions
    308
  - Timing Example 3: Negative Tails
    309
- Instruction Timing Tables
  310
  - Fetch Effective Address
    312
  - Calculate Effective Address
    313
  - MOVE Instruction
    314
  - Arithmetic/Logic Instructions
    315
  - Immediate Arithmetic/Logic Instructions
    317
  - Binary-Coded Decimal and Extended Instructions
    318
  - Shift/Rotate Instructions
    319
  - Bit Manipulation Instructions
    320
  - Control Instructions
    321
  - Save and Restore Operations
    322

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Motorola CPU32 Reference Manual

Motorola CPU32 Reference Manual (367 pages)

M68300 Series CENTRAL PROCESSOR UNIT

Brand: Motorola | Category: Computer Hardware | Size: 10.67 MB

Table of Contents

Table of Contents
6
Overview
16
Features
17
Virtual Memory
17
Loop Mode Instruction Execution
18
Vector Base Register
18
Enhanced Addressing Modes
19
Instruction Set
20
Low-Power Stop Instruction
22
Processing States
22
Privilege States
22
Block Diagram
23
Programming Model
24
Architecture Summary
24
Registers
26
Data Types
27
Organization in Registers
27
Data Registers
27
Address Registers
29
Control Registers
29
Organization in Memory
30
Data Organization and Addressing Capabilities
32
Program and Data References
33
Notation Conventions
33
Implicit Reference
34
Memory Addressing Modes
35
Effective Address
35
Register Direct Mode
35
Data Register Direct
35
Address Register Direct
35
Address Register Indirect
36
Address Register Indirect with Postincrement
36
Address Register Indirect with Predecrement
36
Address Register Indirect with Displacement
37
Address Register Indirect with Index (8-Bit Displacement)
37
Address Register Indirect with Index (Base Displacement)
39
Special Addressing Modes
39
Program Counter Indirect with Displacement
39
Program Counter Indirect with Index (8-Bit Displacement)
40
Program Counter Indirect with Index (Base Displacement)
40
Absolute Short Address
41
Absolute Long Address
42
Immediate Data
42
Effective Address Encoding Summary
43
Programming View of Addressing Modes
45
Addressing Capabilities
46
General Addressing Mode Summary
47
M68000 Family Addressing Capability
49
Other Data Structures
50
System Stack
50
User Stacks
51
Queues
52
M68000 Family Compatibility
54
Instruction Set
54
New Instructions
55
Low-Power STOP (LPSTOP)
55
Unimplemented Instructions
55
Instruction Format
56
Notation
57
Instruction Summary
59
Condition Code Register
59
Data Movement Instructions
61
Integer Arithmetic Operations
62
Shift and Rotate Instructions
64
Bit Manipulation Instructions
65
Binary-Coded Decimal (BCD) Instructions
66
Program Control Instructions
66
System Control Instructions
68
Condition Tests
70

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