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1
VCC
3
GND
7
CCLK
9
DONE
11
DIN
13
PROG
15
INIT
17
RST
J2A
8
SW2
INIT
XC4003E FPGA and Socket (U5)
Hardware User Guide
SW2
RN2
J2B
1K
2
2
1
RT
4
4
3
RD
6
6
5
TRIG
10
TDI
J10
12
TCK
14
1
TMS
16
2
CLKI
18
3
CLKO
1
8
N
O
C
U
13
T
PGCK1
14
I/O
15
Y1
TDI-I/O
16
TCK-I/O
17
TMS-I/O
18
I/O
1
2
19
I/O
1
2
20
I/O
3
4
3
4
23
I/O
24
I/O
5
6
25
I/O
5
6
26
I/O
7
8
27
I/O
7
8
28
I/O
29
SGCK2
30
RN8
M1
RN9
1K
1K
32
M0
+5
RN3
1
1
1
1
1
1
1
27K
CUT
5
6
7
8
4
9
2
OPTION
1
2
J7
RN13
560
RN14
560
D17
MBR030
9
SW6
SW5
SW4
PROG
RESET
SPARE
+5
Figure 3-6 XC4003E Schematic
The XC4003E FPGA occupies socket U5 on the demonstration board.
FPGA Design Demonstration Board
+5
1
1
1
3
2
1
RN4
4.7K
4
6
2
1
9
1
7
1
CLK
DOUT
DIN
U5
XC4003E
PGCK3
PROG
2
4
6
8
2
4
6
8
2
8
6
4
8
6
4
2
1
3
5
7
1
3
5
7
1
7
5
3
7
5
3
1
1
1
7
6 4 2
1 9
0 5
7
6 4 2
1 9
0 5
8
3
8
U7
HPSP5551
+5
D9
2
2
2
2
2
2
2
2
LD101VR
1
1
1
1
1
1
1
1
RN18
RN19
1
3
5
7
1
3
5
7
560
73
72
2
4
6
8
2
4
6
8
71
70
I/O
69
I/O
68
I/O
67
I/O
66
I/O
65
I/O
62
I/O
61
I/O
60
I/O
59
I/O
58
I/O
57
56
I/O
55
1
0
SW2
RST
7
SW2
2
15
MPE
SW2
3
14
SPE
RN15
560
RN12
560
+5
U1, U2
7, 8
U3
3
U4
18, 52
U5
2, 11, 33, 42, 54,
U8
HPSP5551
63, 74
3
D16
1
560
6
SW1
INP
1
INP3
R4
R5
1K
1K
8
RN4
4.7K
1
U2
1
DATA
2
CLK
6
CEO
3
OE/R
4
CE
1765
R3
100K
GND
5
2
1, 35
1, 12, 21, 31, 43, 52,
43, 52, 64, 76
X4728
3-13
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