Mclk-Master Clock (Sw1-7); Dout-Data Out (Sw1-8); Xchecker/Parallel Cable Iii Connector J1 - Xilinx MultiLINX Series Hardware User's Manual

MCLK-Master Clock (SW1-7)

DOUT-Data Out (SW1–8)

XChecker/Parallel Cable III Connector J1

Pin Name
a
J1–1 VCC
a
J1–3 GND
Hardware User Guide
To configure from the onboard serial PROM, these switches must be
off. This places the FPGA in master serial mode.
When this switch is on, it connects the XC4003E configuration clock
(pin 73) to the configuration clock on the XC3020A (pin 60). This
connection is used to configure FPGAs in a daisy chain with the
XC4003E at the head.
When this switch is on, it connects the XC4003E data out line (pin 72)
to the data in line of the XC3020A. This connection configures FPGAs
in a daisy chain with the XC4003E at the head.
Note MCLK and DOUT should only be used to configure the FPGAs
in a daisy chain.
The following table describes the pins and functions of the
XChecker/Parallel Cable III J1 connector.
Table 3-7 XChecker/Parallel Cable III Connector J1
Function
Supplies +5 V to the
XChecker Cable.
Supplies ground
reference to
XChecker Cable.
FPGA Design Demonstration Board
Pin Name
J1–2 RT
J1–4 RD
Function
Allows XChecker
Cable to trigger a read-
back of the XC3020A.
Connects to XC3020A
pin 26.
Used by XChecker
Cable for readback
data. Connects to
XC3020A pin 25.
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