Xchecker Baud Rates; Configuring Cplds With The Xchecker Cable - Xilinx MultiLINX Series Hardware User's Manual

Hardware User Guide

XChecker Baud Rates

Configuring CPLDs With the XChecker Cable

1-18
Communication between your host system and the XChecker Cable
is dependent on host system capability. The XChecker Cable supports
several Baud rates and platforms, as shown in the following table.
Table 1-4 Valid Baud Rates
Platform
IBM® PC
NEC PC
SUN®
HP 700
X indicates applicable baud rate
The JTAG Programmer should be used to program in JTAG mode.
When you configure a CPLD with the XChecker Cable, connections
between the cable assembly and the target system use only six of the
sixteen leads. For connection to JTAG boundary-scan systems you
need only ensure that the VCC, GND, TDI, TCK, TMS and RD (TDO)
pins are connected.
Note TRST is an optional pin in the JTAG (IEEE 1149.1) specification,
and is not used by XC9500 CPLDs (If any of your non-Xilinx parts
have a TRST pin, the pin should be connected to VCC).
Once installed properly, the connectors provide power to the cable
and allow download and readback of configuration data. The
following table describes the CPLD pin connections to the target
circuit board.
Table 1-5 XChecker Cable Pin Connections for CPLDs
Name Function
VCC Power – Supplies VCC (5
V, 100 mA, typically) to the
cable
GND Ground – Supplies ground
reference to the cable
9600 19200
X X
X
X X
X X
Xilinx Development System
38400 115.2K
X X
X
X X
Connections
To target system VCC
To target system
ground