Mode Switch Settings - Xilinx MultiLINX Series Hardware User's Manual

Mode Switch Settings

Hardware User Guide
N = approximately 0.35 for TTl threshold
= approximately 0.75 for CMOS threshold
when the FPGA allows each capacitor to discharge during the oppo-
site timing phase.
This section describes the SW1 and SW2 switch settings for config-
uring the XC3020A and XC4003E devices.
•
From the XChecker/Parallel Cable III
•
From the serial PROM (single program)
•
From the serial PROM (multiple program)
•
In a daisy chain
The following table lists the names and positions of the SW1 and SW2
switches for configuring the XC3020A FPGA from the XChecker or
Parallel Cable III.
Table 3-8 Configuring the XC3020A from the XChecker/Parallel
Cable III
Switch Name
SW1–1 INP
SW1–2 MPE
SW1–3 SPE
SW1–4 M0
SW1–5 M1
SW1–6 M2
SW1–7 MCLK
SW1–8 DOUT
X indicates don't care
FPGA Design Demonstration Board
Position Switch
X SW2–1
OFF SW2–2
OFF SW2–3
ON SW2–4
ON SW2–5
ON SW2–6
OFF SW2–7
OFF SW2–8
Name Position
PWR X
MPE X
SPE X
M0 X
M1 X
M2 X
RST
INIT OFF
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