Schematic With Vhdl Macro Design - Xilinx MultiLINX Series Hardware User's Manual

Hardware User Guide
4-6
Series™ software. Use these tutorial designs to learn the ISP design
flow.

Schematic With VHDL Macro Design

JCT_SVHD is a simple 8-bit Johnson counter
DESIGN FLOW: Schematic (JCT_SVH1.SCH) with XVHDL
macro (JCOUNTER.VHD)
TARGET DEVICE: XC9536-VQ44 (any speed)
I/O Pins:
CLK : input free-running clock
Q0-Q7 : counter outputs
OPERATION:
The counter is triggered on rising edge of the
clock(CLK).
The following is the sequence of states on outputs
Q Q7-Q0:
00000000
00000001
00000011
00000111
00001111
00011111
00111111
01111111
11111110
11111110
11111100
11111000
11110000
11100000
11000000
10000000
00000000 (repeats)
SIMULATION WAVEFORMS:
Xilinx Development System