Mpe-Multiple Program Enable (Sw1-2); Spe-Single Program Enable (Sw1-3); M0, M1, M2-Mode Pins (Sw1-4,5,6) - Xilinx MultiLINX Series Hardware User's Manual

Hardware User Guide

MPE-Multiple Program Enable (SW1-2)

SPE-Single Program Enable (SW1-3)

M0, M1, M2-Mode Pins (SW1-4,5,6)

3-20
1K
XC3020A
Figure 3-8 Configuration Switch SW1
When MPE is on and SPE is off, the configuration PROM (U1) is reset
by the RESET pushbutton (SW4). Configuration must be set to the
master serial mode. After a Reset or powerup, the first bitstream
stored in the serial PROM is loaded into the XC3020A FPGA. IF you
press RESET, the serial PROM address pointer is reset. If you press
PROG (SW6), the XC3020A is loaded with the first bitstream again. If
you press PROG, and do not press RESET, the XC3020A is loaded
with the next bitstream stored in the serial PROM. The number of
bitstreams that can be sequentially loaded is limited by the size of the
serial PROM.
When SPE is on and MPE is off, the configuration PROM (U1) is reset
by the XC3020A's INIT output, which is driven Low whenever you
press PROG (SW6). The first bitstream stored in the serial PROM is
loaded into the XC3020A FPGA.
Note MPE and SPE must not be on at the same time. MPE and SPE
are only used in conjunction with the serial PROMs. The serial
PROMs must be configured as OE/RESET to allow MPE and SPE to
function properly.
To configure the XC3020A using the XChecker/Parallel Cable III
these switches must be on. This places the FPGA in slave serial mode.
+5V
SW1-1
1K
4.7K
Xilinx Development System
XC4003E
X4691