Example 2: Vhdl Design Entry - Xilinx MultiLINX Series Hardware User's Manual

Example 2: VHDL Design Entry

Hardware User Guide
JCT_FUNC : functional simulation of design before
implementation.
JCT_TIME : timing simulation results after
implementation.
TUTORIAL:
This project is used as one of the example designs
described in the CPLD Design Flow tutorial in the
Foundation Series On-Line Help System.
DEMO BOARD:
The JEDEC programming file produced by this
project
can be downloaded into the CPLD Demo Board
(HW-CPLD-DEMOBD).
Example 2 shows the same design, done in VHDL while using Xilinx
Foundation software.
library IEEE;
use IEEE.std_logic_1164.all
library metamor;
use metamor.attributes.all;
entity jcounter is
port (
clk:in STD_LOGIC;
Dout: buffer STD_LOGIC_VECTOR (7 downto 0)
);
CPLD Design Demonstration Board
4-7