Jumper J7 And Tiepoints J10 (1-3); Serial Prom Socket (U2) - Xilinx MultiLINX Series Hardware User's Manual

Pin Name
J2-15 INIT
J2-17 RST
a. Denotes pins supported by the Parallel Cable III
b. No pin connection

Jumper J7 and Tiepoints J10 (1-3)

Serial PROM Socket (U2)

Hardware User Guide
Table 3-6 XChecker/Parallel Cable III Connector J2
Function
Goes Low if CRC
error occurs during
configuration.
Connects to
XC4003E INIT pin
41.
Connects to jumper
J7. If connected,
allows XChecker
Cable to provide a
Reset input (same as
pressing the Reset
button).
The D/P wire from the FPGA header on the Parallel Cable III is
connected to J2-9 DONE pin.
Jumper J7 allows the XChecker signal RST on J2-17 to drive the reset
line on the demonstration board. Tiepoint pins jumper the following
XChecker signals into the circuit. Tiepoint J10-1 connects to TRIG on
J2-6; Tiepoint J10-2 connects to CLK1 on J2-16; and, Tiepoint J10-3
connects to CLK0 on J2-18. See the preceding table for more details on
the cable and pin connections.
This serial PROM configures the XC4003E or the XC4003E and
XC3020A connected in a daisy chain. The configuration mode must
be in the master serial mode to configure from the serial PROM.
FPGA Design Demonstration Board
Pin Name
J2-16 CLK1
J2-18 CLK0
Function
A system clock input to
XChecker Cable to be
controlled and output on
CLK0.
Connects to tiepoint J10-
2.
A system clock output
controlled by XChecker
Cable. Used to single-
step or burst clocks to
the XC4003E.
Connects to tiepoint J10-
3.
3-17