Configuring Fpgas With The Parallel Cable Iii - Xilinx MultiLINX Series Hardware User's Manual

Configuring FPGAs With the Parallel Cable III

Hardware User Guide
Table 1-3 Parallel Cable III CPLD Pin Connections
Name Function
TDI Test Data Input – this
signal is used to transmit
serial test instructions and
data.
TMS Test Mode Select – this
signal is decoded by the
JTAG state machine to
control test operations.
Note TRST is an optional pin in the JTAG (IEEE 1149.1) specification,
and is not used by XC9500 CPLDs. If any of your non-Xilinx parts
have a TRST pin, the pin should be connected to VCC
This section details the connections needed to configure FPGAs with
the Parallel Cable III.
The following figures show which pins to connect, depending on
your chosen FPGA device. For descriptions of each pin, see Table 3-
6and Table 3-7 of the "FPGA Design Demonstration Board" chapter.
Note If you are using the Xilinx FPGA Design Demonstration Board,
see the "Mode Switch Settings" section of the "FPGA Design Demon-
stration Board" chapter for specific configuration information.
Connect the flying wires to XC4000 FPGAs as shown in the following
figure.
Cable Hardware
Connections
Connect to system TDI
pin.
Connect to system TMS
pin.
1-13