Pin Connection Considerations - Xilinx MultiLINX Series Hardware User's Manual

Hardware User Guide

Pin Connection Considerations

1-20
The following figures show which pins to connect, depending on
your chosen FPGA device. For descriptions of each pin, see Table 3-
6and Table 3-7 of the "FPGA Design Demonstration Board" chapter.
Use Header 1 (see
target system for configuring FPGAs. When configuring XC4000
FPGAs, the RST (Reset) wire is not used as shown in the following
figure.
Not Used
Figure 1-11 XChecker Connections to XC4000 Device
To configure XC3000 FPGAs, the PROG wire is not used. This is
shown in the following figure. In both cases, the FPGA must be in the
Serial Slave Mode.
Not Used
Figure 1-12 XChecker Connections to XC3000 Device
The following adjustments will make the process of connecting and
downloading easier.
Figure 1-9) to connect the XChecker Cable to the
VCC
GND
CCLK
D/P
DIN
PROG
INIT
XChecker with Header 1
VCC
GND
CCLK
D/P
DIN
INIT
RST
XChecker with Header 1
VCC
GND
CCLK
DONE
DIN
PROG
INIT
XC4000 FPGA in Slave Serial Mode
Target System
VCC
GND
CCLK
D/P
DIN
INIT
RESET
XC3000 FPGA in Slave Serial Mode
Target System
Xilinx Development System
X8323
X8324