Jtag Mode (Xc9000, Virtex, Spartan, Xc5200, Xc4000) - Xilinx MultiLINX Series Hardware User's Manual

Hardware User Guide
2-18
4 3
CS0 (CS) D0
CS1 D1
CS2 D2
CLK2-IN D3
CLK2-OUT D4
WS D5
RS (RDWR) D6
D7
RDY/BUSY
Circuit Board
System Clock (x)
System Clock (y)
(optional)
NOTE: Pull-up resistors are 4.7k ohm.
Figure 2-10 SelectMAP Mode (Virtex with Asynchronous
Probing)
JTAG Mode (XC9000, Virtex, Spartan, XC5200,
XC4000)
The following figure shows in detail the JTAG Mode connections for
XC9000, Virtex, Spartan, XC5200, and XC4000 devices.
MultiLINX Connectors
RT PWR
RD (TDO) GND
TRIG
CCLK
TDI DONE (D / P)
TCK DIN
TMS PROG
CLK1-IN INIT
CLK1-OUT RST
2 1
(optional)
XILINX device
BUSY/DOUT
WRITE
CS User Logic
flip-flops & latches,
LUTRAMS,
& block RAMS
INIT
PROGRAM
CAPTURE
DONE
GCK (x)
Capture Control
CAPCLK Logic CCLK
GCK (y)
VCC VCC
Vcco
Vcco
Vcco
Xilinx Development System
X8935