Configuring Fpgas With The Xchecker Cable - Xilinx MultiLINX Series Hardware User's Manual

Configuring FPGAs With the XChecker Cable

Hardware User Guide
Table 1-5 XChecker Cable Pin Connections for CPLDs
Name Function
RD (TDO) Read Data – Reads back
data from the target
system is read at this pin.
TDI Test Data In – this signal is
used to transmit serial test
instructions and data.
TCK Test Clock – this clock
drives the test logic for all
devices on boundary-scan
chain.
TMS Test Mode Select – this
signal is decoded by the
TAP controller to control
test operations.
CLKI Not used.
CLKO Not used.
CCLK Not used.
D/P Not used.
DIN Not used.
PROG Not used.
INIT Not used.
RST Not used.
RT Not used.
TRIG Not used.
This section details the connections needed to configure FPGAs with
the XChecker Cable.
Note If you are using the Xilinx FPGA Design Demonstration Board,
see the "Demonstration Board Operation" section of the "FPGA
Design Demonstration Board" chapter for specific configuration
information.
Cable Hardware
Connections
Connect to system
TDO pin.
Connect to system TDI
pin.
Connect to system TCK
pin.
Connect to system TMS
pin.
Unconnected.
Unconnected.
Unconnected.
Unconnected.
Unconnected.
Unconnected.
Unconnected.
Unconnected.
Unconnected.
Unconnected.
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