Foundation Design Tutorial; Example I: Schematic Design Entry - Xilinx MultiLINX Series Hardware User's Manual

SW1
ON
OFF
J1
VCC
GND
TCK
TDO
TDI
TMS
C3

Foundation Design Tutorial

Example I: Schematic Design Entry

Hardware User Guide
J2
R
+5V
33 32 31 30 29 28 27 26
C1
34
35
36
37
38
R
39
XC9536
40
41
U1
42
43
44
1 2 3 4 5 6 7
R9
ISP DEMO BOARD
U3
Figure 4-2 CPLD ISP Demonstration Board
All pins of the XC9536 device are connected to through-hole pads on
the PCB, numbered 1 to 44. Header Rows of 0.025 inch square posts
(on 0.10 inch centers) can be installed at these locations to provide
connection points for application circuitry.
The Xilinx Foundation Software Series contains the CPLD Jcounter
tutorial, which includes the following five design entry methods.
•
JCT_SCH (schematic only)
•
JCT_ABL (ABEL only)
•
JCT_SABL (schematic with ABEL macro)
•
JCT_VHD (VHDL only)
•
JCT_SVHD (schematic with VHDL macro)
Example 1 shows the readme.txt file that is located in the project
directories of the Jcounter tutorial designs in the Xilinx Foundation
CPLD Design Demonstration Board
J3
U2
+9V
C2
25 24 23
D1
22
R1
IN
21
20
19
18
17 C4
16
15
14
13
12
R8
D8
8 9 10 11
OUT
+5V
GND
+5V
GND
X8163
4-5