Figure D-17 Sci Status And Clock Control Registers (Ssr, Sccr - Motorola DSP56309 User Manual

Application:
SCI
Overrun Error Flag
0 = No error
1 = Overrun detected
Parity Error Flag
0 = No error
1 = Incorrect Parity detected
Framing Error Flag
0 = No error
1 = No Stop Bit detected
Received Bit 8
0 = Data
1 = Address
SCI Status Register (SSR)
Address X:$FFFF93
Read Only
Reset = $000003
Clock Divider Bits CD11 Ð CD0)
TCM RCM TX Clock RX Clock SCLK Pin
0 0 Internal
0 1 Internal
1 0 External
1 1 External
Transmitter Clock Mode/Source
0 = Internal clock for Transmitter
1 = External clock from SCLK

Figure D-17 SCI Status and Clock Control Registers (SSR, SCCR)

MOTOROLA
23 7 6
*
R8 FE
0
$0
*
= Reserved, Program as 0
SCI Status Register (SSR)
Internal Output Synchronous/Asynchronous
External Input Asynchronous only
Internal Input Asynchronous only
External Input Synchronous/Asynchronous
Receiver Clock Mode/Source
0 = Internal clock for Receiver
1 = External clock from SCLK
SCI Clock Prescaler
0 = Ö1 1 = Ö 8
23 15 14 13 12 11 10
*
TCM RCM SCP COD CD11
0
SCI Clock Control Register (SCCR)
DSP56309UM/D
Idle Line Flag
0 = Idle not detected
1 = Idle State
5 4 3 2 1 0
PE OR IDLE RDRF TDRE TRNE
$3
Clock Divider Bits CD11 Ð CD0)
Mode CD11 Ð CD0
Clock Out Divider
0 = Divide clock by 16 before feed to SCLK
1 = Feed clock to directly to SCLK
9 8 7
CD10 CD9 CD8 CD7
Programming Reference
Date:
Programmer:
Sheet 2 of 3
Receive Data Register Full
0 = Receive Data Register Empty
1 = Receive Data Register Full
Transmitter Data Register Empty
0 = Transmitter Data Register full
1 = Transmitter Data Register empty
Transmitter Empty
0 = Transmitter full
1 = Transmitter empty
I Rate
cyc
$000 I /1
cyc
$001 I /2
cyc
$002 I /3
cyc
¥ ¥
¥ ¥
¥ ¥
$FFE I /4095
cyc
$FFF I /4096
cyc
6 5 4 3 2
CD6 CD5 CD4 CD3 CD2
*
= Reserved, Program as 0
1 0
CD1 CD0
D-31