Motorola DSP56309 User Manual page 231

Serial Communication Interface (SCI)
SCI Programming Model
The length and format of the serial word are defined by the WDS0, WDS1, and WDS2
control bits in the SCR. The clock source is defined by the receive clock mode (RCM)
select bit in the SCR.
In synchronous mode, the start bit, the eight data bits, the address/data indicator bit
and/or the parity bit, and the stop bit are received in that order. Data bits are sent LSB
first if SSFTD is cleared, and MSB first if SSFTD is set. In synchronous mode, the
synchronization is provided by gating the clock.
In either synchronous or asynchronous mode, when a complete word has been clocked
in, the contents of the shift register can be transferred to the SRX and the flags; RDRF, FE,
PE, and OR are changed appropriately. Because the operation of the receive shift register
is transparent to the DSP, the contents of this register are not directly accessible to the
programmer.
8.3.4.2 SCI Transmit Registers
The transmit data register is a one byte-wide register mapped into four addresses as
STXL, STXM, STXH, and STXA. In asynchronous mode, when data is to be transmitted,
STXL, STXM, and STXH are used. When STXL is written, the low byte on the data bus is
transferred to the STX. When STXM is written, the middle byte is transferred to the STX.
When STXH is written, the high byte is transferred to the STX. This structure makes it
easy for the programmer to unpack the bytes in a 24-bit word for transmission. TDXA
should be written in the 11-bit asynchronous multidrop mode when the data is an
address and it is desired that the ninth bit (the address bit) be set. When STXA is written,
the data from the low byte on the data bus is stored in it. The address data bit is cleared
in the 11-bit asynchronous multidrop mode when any of STXL, STXM or STXH is
written. When either STX (STXL, STXM, or STXH) or STXA is written, TDRE is cleared.
The transfer from either STX or STXA to the transmit shift register occurs automatically,
but not immediately, when the last bit from the previous word has been shifted out; that
is, the transmit shift register is empty. Like the receiver, the transmitter is
double-buffered. However, a 2 to 4 serial clock cycle delay occurs between when the
data is transferred from either STX or STXA to the transmit shift register and when the
first bit appears on the TXD signal. (A serial clock cycle is the time required to transmit
one data bit). The transmit shift register is not directly addressable, and a dedicated flag
for this register does not exist. Because of this fact and the 2 to 4 cycle delay, two bytes
cannot be written consecutively to STX or STXA without polling, as the second byte
might overwrite the first byte. The TDRE flag should always be polled prior to writing
STX or STXA to prevent overruns unless transmit interrupts have been enabled. Either
STX or STXA is usually written as part of the interrupt service routine. An interrupt is
generated only if TDRE is set. The transmit shift register is indirectly visible via the
TRNE bit in the SSR.
8-20 DSP56309UM/D MOTOROLA