Motorola DSP56309 User Manual page 159

Host Interface (HI08)
Servicing the Host Interface
The host processor first performs a data read transfer to read the ISR, as in Figure 6-16.
This convention allows the host processor to assess the status of the HI08 and perform
the appropriate actions.
Generally, after the appropriate data transfer has been made, the corresponding status
bit is updated to reflect the transfer.
¥ If RXDF is set, the receive data register is full, and the host processor can perform
a data read.
¥ If TXDE is set, the transmit data register is empty, and the host processor can
perform a data write.
¥ If TRDY is set, the transmit data register is empty. This implies that the receive
data register on the DSP side is also empty. Data written by the host processor to
the HI08 is transferred directly to the DSP side.
¥ If (HF2 and HF3)
indicate that an application-specific state within the DSP56309 has been reached.
Intervention by the host processor may be required.
¥ If HREQ is set, the HREQ/TRQ signal has been asserted, and the DSP56309 is
requesting the attention of the host processor. One of the previous four conditions
exists.
After the appropriate data transfer has been made, the corresponding status bit is
updated to reflect the transfer.
If the host processor has issued a command to the DSP56309 by writing to the CVR and
setting the HC bit, it can read the HC bit in the CVR to determine whether the command
has been accepted by the interrupt controller in the DSP core. When the command has
been accepted for execution, the HC bit is cleared by the interrupt controller in the DSP
core.
6.7.3 Servicing Interrupts
If either HREQ/HTRQ or the HRRQ signal or both are connected to the host processorÕs
interrupt input, the HI08 can request service from the host processor by asserting one of
these signals. The HREQ/HTRQ and/or the HRRQ signal is asserted when TXDE is set
and/or RXDF is set and the corresponding enable bit (TREQ or RREQ, respectively) is
set. This situation appears in Figure 6-16.
6-32
¹
0, depending on how the host flags have been used, this may
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