Motorola DSP56309 User Manual page 255

Triple Timer Module
Triple Timer Module Programming Model
9.3.4.7 Direction (DIR) Bit 11
The DIR bit determines the behavior of the TIO signal when it is used as a GPIO signal.
When the DIR bit is set, the TIO signal is an output; when the DIR bit is cleared, the TIO
signal is an input. The TIO signal can be used as a GPIO signal only when all of the
TC[3:0] bits are cleared. If any of the TC[3:0] bits are set, then the GPIO function is
disabled and the DIR bit has no effect.
The DIR bit is cleared by a hardware RESET signal or a software RESET instruction.
9.3.4.8 Data Input (DI) Bit 12
The DI bit reflects the value of the TIO signal. If the INV bit is set, the value of the TIO
signal is inverted before it is written to the DI bit. If the INV bit is cleared, the value of
the TIO signal is written directly to the DI bit.
DI is cleared by a hardware RESET signal or a software RESET instruction.
9.3.4.9 Data Output (DO) Bit 13
The DO bit is the source of the TIO value when it is a data output signal. The TIO signal
is data output when GPIO mode is enabled and DIR is set. A value written to the DO bit
is written to the TIO signal. If the INV bit is set, the value of the DO bit is inverted when
written to the TIO signal. When the INV bit is cleared, the value of the DO bit is written
directly to the TIO signal. When GPIO mode is disabled, writing the DO bit has no effect.
The DO bit is cleared by a hardware RESET signal or a software RESET instruction.
9.3.4.10 Prescaler Clock Enable (PCE) Bit 15
The PCE bit is used to select the prescaler clock as the timer source clock. When the PCE
bit is cleared, the timer uses either an internal (CLK/2) signal or an external (TIO) signal
as its source clock. When the PCE bit is set, the prescaler output is used as the timer
source clock for the counter regardless of the timer operating mode. To insure proper
operation, the PCE bit should be changed only when the timer is disabled (when the TE
bit is cleared). Which source clock is used for the prescaler is determined by the PS[1:0]
bits of the TPLR. A timer can be clocked by a prescaler clock that is derived from the TIO
of another timer.
9.3.4.11 Timer Overflow Flag (TOF) Bit 20
The TOF bit is set to indicate that counter overflow has occurred. This bit is cleared by
writing a 1 to the TOF bit. Writing a 0 to the TOF bit has no effect. The bit is also cleared
when the timer overflow interrupt is serviced.
The TOF bit is cleared by a hardware RESET signal, a software RESET instruction, the
STOP instruction, or by clearing the TE bit to disable the timer.
9-14 DSP56309UM/D MOTOROLA