Table 8-1 Word Formats - Motorola DSP56309 User Manual

Serial Communication Interface (SCI)
SCI Programming Model
8.3.1 SCI Control Register (SCR)
The SCR is a 24-bit, read/write register that controls the serial interface operation.
Seventeen of the twenty-four bits are currently defined. Each bit is described in the
following paragraphs.
8.3.1.1 SCR Word Select (WDS[0:2]) Bits 0Ð2
The word select WDS[0:2] bits select the format of transmitted and received data. Format
modes are listed in Table 8-1 below and shown in Figure 8-4 on page 8-6.
WDS2 WDS1
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Asynchronous modes are compatible with most UART-type serial devices and support
standard RS232C communication links. Multidrop asynchronous mode is compatible
with the MC68681 DUART, the M68HC11 SCI interface, and the Intel 8051 serial
interface. Synchronous data mode is essentially a high-speed shift register used for I/O
expansion and stream-mode channel interfaces. A gated transmit and receive clock
compatible with the Intel 8051 serial interface mode 0 makes it possible for you to
synchronize data.
When odd parity is selected, the transmitter counts the number of 1s in the data word. If
the total is not an odd number, the parity bit is set, thus producing an odd number. If the
receiver counts an even number of 1s, an error in transmission has occurred. When even
parity is selected, an even number must result from the calculation performed at both
ends of the line, or an error in transmission has occurred.
8-8

Table 8-1 Word Formats

WDS0 Mode
0 0 8-bit synchronous data (shift register mode)
1 1 Reserved
0 2 10-bit asynchronous (1 start, 8 data, 1 stop)
1 3 Reserved
0 4 11-bit asynchronous
(1 start, 8 data, 1 even parity, 1 stop)
1 5 11-bit asynchronous
(1 start, 8 data, 1 odd parity, 1 stop)
0 6 11-bit multidrop asynchronous
(1 start, 8 data, 1 data type, 1 stop)
1 7 Reserved
DSP56309UM/D
Word Formats
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