Motorola DSP56309 User Manual page 169

24-bit digital signal processor
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Enhanced Synchronous Serial Interface (ESSI)
ESSI Data and Control Signals
¥ Audio enhancements
Ð Three transmitters per ESSI (for six-channel surround sound)
¥ General enhancements
Ð Can trigger DMA interrupts (receive or transmit)
Ð Separate exception enable bits
¥ Other Changes
Ð One divide by 2 removed from the internal clock source chain
Ð CRA (PSR) bit definition is reversed
Ð Gated clock mode not available
7.3
ESSI DATA AND CONTROL SIGNALS
Three to six signals are required for ESSI operation, depending on the operating mode
selected. The serial transmit data (STD) signal and serial control (SC0 and SC1) signals
are fully synchronized to the clock if they are programmed as transmit-data signals.
7.3.1
Serial Transmit Data (STD) Signal
The STD signal is used for transmitting data from the TX0 serial transmit shift register.
STD is an output when data is being transmitted from the TX0 shift register. With an
internally generated bit clock, the STD signal becomes a high impedance output signal
for a full clock period after the last data bit has been transmitted. If sequential data
words are being transmitted, the STD signal does not assume a high-impedance state.
The STD signal can be programmed as a GPIO signal (P5) when the ESSI STD function is
not being used.
7.3.2
Serial Receive Data Signal (SRD)
The SRD signal receives serial data and transfers the data to the ESSI receive shift
register. SRD can be programmed as a GPIO signal (P4) when the ESSI SRD function is
not being used.
The ESSI block diagram is shown in Figure 7-1.
7-4
DSP56309UM/D
MOTOROLA

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