Motorola DSP56309 User Manual page 176

7.4.1 ESSI Control Register A (CRA)
The ESSI control register A (CRA) is one of two 24-bit, read/write control registers used
to direct the operation of the ESSI. The CRA controls the ESSI clock generator bit and
frame sync rates, word length, and number of words per frame for the serial data. The
CRA control bits are described in the following paragraphs; see also Figure 7-2 on
page 7-9.
7.4.1.1 CRA Prescale Modulus Select PM[7:0] Bits 7Ð0
The PM[7:0] bits specify the divide ratio of the prescale divider in the ESSI clock
generator. A divide ratio from 1 to 256 (PM = $0 to $FF) can be selected. The bit clock
output is available at the transmit clock signal (SCK) and/or the receive clock (SC0)
signal of the DSP. The bit clock output is also available internally for use as the bit clock
to shift the transmit and receive shift registers. The ESSI clock generator functional
diagram is shown in Figure 7-9. F
frequency as the CLKOUT signal, when that signal is enabled). Careful choice of the
crystal oscillator frequency and the prescaler modulus allows generation of the
industry-standard codec master clock frequencies of 2.048 MHz, 1.544 MHz, and
1.536 MHz. Both the hardware RESET signal and the software RESET instruction clear
PM[7:0].
7.4.1.2 CRA Reserved Bits 8Ð10
These bits are reserved. They are read as 0 and should be written with 0.
7.4.1.3 CRA Prescaler Range (PSR) Bit 11
The PSR controls a fixed divide-by-eight prescaler in series with the variable prescaler.
This bit is used to extend the range of the prescaler for those cases where a slower bit
clock is desired. When PSR is set, the fixed prescaler is bypassed. When PSR is cleared,
the fixed divide-by-eight prescaler is operational; see Figure 7-9 on page 7-12.
Note: This definition is reversed from that of the 560xx SSI.
The maximum allowed internally generated bit clock frequency is the internal DSP56309
clock frequency divided by 4; the minimum possible internally generated bit clock
frequency is the DSP56309 internal clock frequency divided by 4096. Both the hardware
RESET signal and the software RESET instruction clear PSR.
MOTOROLA
Enhanced Synchronous Serial Interface (ESSI)
is the DSP56309 core clock frequency (the same
core
DSP56309UM/D
ESSI Programming Model
7-11