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External Memory Interface
EMI Programming Model
reading 12-bit or 20-bit words from external memory via a 4-bit data bus, the words
are left-aligned and zero-extended to the right before being transferred to the EDRR.
When 12-bit or 20-bit words are transferred via 8-bit data bus, 16 or 24 bits, are
transferred in both read and write directions. While packing or unpacking, the data
word is held in the EDRB. During memory writes, the data to be written is
transferred from the EDWR to the EDRB for unpacking. The EDRB cannot be
accessed by the DSP directly.
4.2.7
EMI Control/Status Register (ECSR)
The EMI Control/Status Register (ECSR) is a 24-bit read/write register used by the
DSP to control and interrogate the EMI operation. The ECSR bits are shown in
Figure 4-2 and described in the following paragraphs.
Note: If ECSR control bits are changed while the EMI is busy (with the exception of
the ECSR interrupt controls EMWIE, EIS[1:0], and the read trigger select
ERTS), improper operation can result.
4.2.7.1
EMI Data Bus Width (EBW)—Bit 0
The read/write control bit EMI Data Bus Width (EBW) defines the width of the EMI
data bus. When EBW is cleared (EBW = 0), the data bus is 4 bits wide. When EBW is
set (EBW = 1), the data bus is 8 bits wide. The bus width affects the number of
memory accesses and address generation required for a data word transfer. The
number of memory accesses performed by the EMI during a word transfer and the
number of memory locations required for a word storage (for words of different
lengths), in both Relative and Absolute Addressing modes, is shown in Table 4-3 .
Note: EBW is cleared by hardware reset and software reset.
Table 4-3 EMI Memory Accesses and Locations Per Word
Addressing
Bus Width
Relative
Relative
Relative
Relative
Relative
Relative
4-10
Word Length
4
8
4
12
4
16
4
20
4
24
4
16 Data/24 Address
DSP56009 User's Manual
Memory
Memory
locations/
accesses/
word
word
2
2
4
3
4
4
8
5
8
6
8
4
MOTOROLA
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