Motorola DSP56309 User Manual page 263

Triple Timer Module
Timer Operational Modes
This process is repeated until the timer is disabled (i.e., TE is cleared). If the counter
overflows, the TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The
counter contents can be read at any time by reading the TCR.
9.4.2.3 Measurement Input Period (Mode 5)
Bit Settings Mode Characteristics
TC3 TC2 TC1 TC0 Mode Name Function TIO Clock
0 1 0 1 5 Input Period Measurement Input Internal
In this mode, the timer counts the period between the reception of signal edges of the
same polarity across the TIO signal.
Set the TE bit to clear the counter and enable the timer. The value to which the timer is to
count is loaded into the TLR. The value of the INV bit determines whether the period is
measured between consecutive low-to-high (0 to 1) transitions of TIO or between
consecutive high-to-low (1 to 0) transitions of TIO. If INV is set, high-to-low signal
transitions are selected. If INV is cleared, low-to-high signal transitions are selected.
After the first appropriate transition occurs on the TIO input signal, the counter is
loaded with the TLR value on the first timer clock signal received from either the
DSP56309 clock divided by two (CLK/2) or the prescaler clock output. Each subsequent
clock signal increments the counter.
On the next signal transition of the same polarity that occurs on TIO, the TCF bit in the
TCSR is set and a compare interrupt is generated if the TCIE bit is set. The contents of the
counter are loaded into the TCR. The TCR then contains the value of the time that
elapsed between the two signal transitions on the TIO signal.
After the second signal transition, if the TRM bit is set, the TE bit is set to clear the
counter and enable the timer. The counter is loaded with the TLR value on the first timer
clock signal. Each subsequent clock signal increments the counter.
After the second signal transition, if the TRM bit is set, the TE bit is set to clear if the TRM
bit is cleared, the counter continues to be incremented on each timer clock. This process
is repeated until the timer is disabled (i.e., TE is cleared). If the counter overflows, the
TOF bit is set, and if TOIE is set, an overflow interrupt is generated. The counter contents
can be read at any time by reading the TCR.
9-22 DSP56309UM/D MOTOROLA