Figure D-2 Operating Mode Register (Omr - Motorola DSP56309 User Manual

Programming Reference
Application:
Central Processor
External Bus Disable
Stop Delay
Memory Switch Mode
Core-DMA Priority
CDP(1:0) Core-DMA Priority
00 Core vs DMA Priority
01 DMA accesses > Core
10 DMA accesses = Core
11 DMA accesses < Core
Burst Mode Enable
TA Synchronize Select
Bus Release Timing
Stack Extension Space Select
Extended Stack Underflow Flag
Extended Stack Overflow Flag
Extended Stack Wrap Flag
Stack Extension Enable
23 22 21 20 19 18 17 16
* * * SEN WRP EOV EUN XYS
0 0 0
System Stack Control
Status Register (SCS)
Operating Mode Register (OMR)
Read/Write
Reset = $00030X
D-16
MOD(D:A) Reset Vector
0000
X001
X010
X011
X100
X101
X110
X111
1000
15 14 13 12 11 10 9
* * *
0 0 0
Extended Chip Operating
Mode Register (COM)

Figure D-2 Operating Mode Register (OMR)

DSP56309UM/D
Chip Operating Modes
$C00000 Expanded mode
$FF0000 Bootstrap from byte wide memory
$FF0000 Bootstrap through SCI
Ñ Reserved
$FF0000 Host Bootstrap PCI mode (32-bit wide)
$FF0000 Host Bootstrap 16-bit wide UB mode (ISA)
$FF0000 Host Bootstrap 8-bit wide UB mode (dbl strb)
$FF0000 Host Bootstrap 8-bit wide UB mode (sgl strb)
$008000 Expanded mode
8 7
BRT TAS BE CDP1 CDP0 MS
*
= Reserved, Program as 0
X = Latched from levels on Mode pins
Date:
Programmer:
Sheet 2 of 5
Description
6 5 4 3 2 1
SD * EBD MD MC MB
0
Chip Operating Mode
Register (COM)
MOTOROLA
0
MA