Methods Of Entering Debug Mode - Motorola DSP56309 User Manual

On-Chip Emulation Module

Methods of Entering Debug Mode

OSCR, and the DSP56300 core exits debug mode by executing the appropriate command
issued by the external command controller.
Upon exiting debug mode, the counter is decremented after each execution of an
instruction. Interrupts are serviceable then. Moreover, all executed instructions,
including fast interrupt services and the execution of each repeated instruction, cause
the OTC to be decremented. Upon decrementing to 0, the DSP56300 core reenters debug
mode, the trace occurrence bit (TO) in the OSCR register is set, the core status bits
OS[1:0] are set to 11, and the DE signal is asserted to indicate that the DSP56300 core has
entered debug mode and is requesting service.
The OnCE Trace Counter (OTC) is a 16-bit counter that can be read or written through
the JTAG port. If N instructions are to be executed before entering debug mode, the OTC
should be loaded with N Ð 1. The OTC is cleared by a hardware RESET signal.
10.7 METHODS OF ENTERING DEBUG MODE
Entering debug mode is acknowledged by the chip by setting the core status bits OS1
and OS0 and asserting the DE line. This informs the external command controller that
the chip has entered debug mode and is waiting for commands. The DSP56300 core can
disable the OnCE module if the ROM Security option is implemented. If the ROM
security is implemented, the OnCE module remains inactive until a write operation to
the OGDBR is executed by the DSP56300 core.
10.7.1 External Debug Request During RESET Assertion
Holding the DE line asserted during the assertion of RESET causes the chip to enter
debug mode. After receiving the acknowledge, the external command controller must
negate the DE line before sending the first command.
In this case, the chip does not execute any instruction before entering debug
Note:
mode.
10.7.2 External Debug Request During Normal Activity
Holding the DE line asserted during normal chip activity causes the chip to finish the
execution of the current instruction and then enter Debug mode. After receiving the
acknowledge, the external command controller must negate the DE line before sending
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