Hitachi H8S/2646 Hardware Manual page 7

List of Items Revised or Added for This Version
Section Page
2.10.2 Caution to 76, 77
observe when using
bit manipulation
instructions
8.3.10 Number of
207
DTC Execution States
9.4.2 Register 242
Configuration
Table 9-6 Port 3
Register
Configuration
9.9.2 Register 263
Configuration
9.10.3 Pin Functions 269
Table 9-20 Port C
Pin Functions
9.13.1 Overview 281
Figure 9-12 Port F
Pin Functions
Description
Newly added
The BSET, BCLR, BNOT, BST and BIST instructions read data in a unit of byte,
then, after bit manipulation, they write data in a unit of byte. Therefore, caution
must be exercised when executing any of these instructions for registers and
ports that include write-only bits.
The BCLR instruction can be used to clear the flag of an internal I/O register to
0. In that case, if it is clearly known that the pertinent flag is set to 1 in an
interrupt processing routine or other processing, there is no need to read the
flag in advance.
4th line changed as follows
Number of execution states = I · (S
For example, when the DTC vector address table is located in on-chip ROM,
normal mode is set, and data is transferred from the on-chip ROM to an internal
I/O register, the time required for the DTC operation is 14 states. The time from
activation to the end of the data write is 11 states.
Name
Port 3 data direction register
Port 3 data register
Port 3 register
Port 3 open drain control register
15th line changed as follows
In mode 7, if a pin is in the input state in accordance with the settings in the
DDR, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up
for that pin.
(Incorrect)PCDDR
(Correct)PCnDDR
Pin functions in modes 4 to 6
PF7 (input) / ø (output)
PF6 (I/O) / AS (output) / SEG20 (output) / SEG36 * (output)
PF5 (I/O) / RD (output) / SEG19 (output) / SEG35 * (output)
+1) + Σ (J · S
+ K · S
I J K
Abbreviation R/W Initial Value
P3DDR W H'00
P3DR R/W H'00
PORT3 R Undefined
P3ODR R/W H'00
+ L · S ) + M · S
L M
Address*
H'FE32
H'FF02
H'FFB2
H'FE46