Floating-Point Instruction Execution Times - Motorola M68060 User Manual

Instruction Execution Timing
Table 10-24. Miscellaneous Instruction Execution Times (Continued)
Instruction
PLPA (ATC hit)
PLPA (ATC miss)
PFLUSH
PFLUSHN
PFLUSHAN
PFLUSHA
RESET
STOP
SWAP
TRAPF
TRAPcc
TRAPV
UNLK
UNPK
1
For these entries, add the effective address calculation time.
2
For the CPUSH instruction, the operand write figure refers to line-sized transfers.
10.15 FPU INSTRUCTION EXECUTION TIMES
Table 10-25 shows the number of clock cycles required for execution of the floating-point
instructions, including completion of the operation and storing of the result. The number of
operand read and write cycles is shown in parentheses (r/w).
Table 10-25. Floating-Point Instruction Execution Times
Instruction
FPn Dn
FABS 1(0/0) 3(0/0)
FDABS 1(0/0) 3(0/0)
FSABS 1(0/0) 3(0/0)
FADD 3(0/0) 5(0/0)
FDADD 3(0/0) 5(0/0)
FSADD 3(0/0) 5(0/0)
FCMP 1(0/0) 3(0/0)
FDIV 37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
FDDIV 37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
FSDIV 37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
FMOVE
1(0/0) 3(0/0)
,FPx
FDMOVE
1(0/0) 3(0/0)
,FPx
FSMOVE
1(0/0) 3(0/0)
,FPx
FMOVE
— 3(0/0)
FPy,
FMOVE
— 8(0/0)
,FPCR
FMOVE
— 4(0/0)
FPCR,
FINT 3(0/0) 4(0/0)
FINTRZ 3(0/0) 4(0/0)
10-24
Size Register
— 15(0/0)
— 28(0/0)
— 18(0/0)
— 18(0/0)
— 33(0/0)
— 33(0/0)
— 520(0/0)
Word 8(0/0)
Word 1(0/0)
— 1(0/0)
— 1(0/0)
— 1(0/0)
— 1(1/0)
— 2(0/0)
Effective Address, <ea>
(d16,An)
(An) (An)+ –(An)
(d16,PC)
1(1/0) 1(1/0) 1(1/0)
1(1/0) 1(1/0) 1(1/0)
1(1/0) 1(1/0) 1(1/0)
3(1/0) 3(1/0) 3(1/0)
3(1/0) 3(1/0) 3(1/0)
3(1/0) 3(1/0) 3(1/0)
1(1/0) 1(1/0) 1(1/0)
1(1/0) 1(1/0) 1(1/0)
1(1/0) 1(1/0) 1(1/0)
1(1/0) 1(1/0) 1(1/0)
1(0/1) 1(0/1) 1(0/1)
6(1/0) 6(1/0) 6(1/0)
2(0/1) 2(0/1) 2(0/1)
3(1/0) 3(1/0) 3(1/0)
3(1/0) 3(1/0) 3(1/0)
M68060 USER'S MANUAL
Memory Reg -> Dest
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
2(1/1) —
(d8,An,Xi∗SF) (bd,An,XI∗SF)
(d8,PC,Xi∗SF) (bd,PC,XI∗SF)
1(1/0) 2(1/0)
1(1/0) 2(1/0)
1(1/0) 2(1/0)
3(1/0) 4(1/0)
3(1/0) 4(1/0)
3(1/0) 4(1/0)
1(1/0) 2(1/0)
37(1/0) 38(1/0)
37(1/0) 38(1/0)
37(1/0) 38(1/0)
1(1/0) 2(1/0)
1(1/0) 2(1/0)
1(1/0) 2(1/0)
1(1/0) 2(0/1)
6(1/0) 7(1/0)
2(1/0) 3(0/1)
3(1/0) 3(1/0)
3(1/0) 3(1/0)
Source -> Reg
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(xxx).WL #<imm>
3(1/0) 2(1/0) 2(0/0)
3(1/0) 2(1/0) 2(0/0)
3(1/0) 2(1/0) 2(0/0)
5(1/0) 4(1/0) 4(0/0)
5(1/0) 4(1/0) 4(0/0)
5(1/0) 4(1/0) 4(0/0)
3(1/0) 2(1/0) 2(0/0)
39(1/0) 38(1/0) 38(0/0)
39(1/0) 38(1/0) 38(0/0)
39(1/0) 38(1/0) 38(0/0)
3(1/0) 2(1/0) 1(0/0)
3(1/0) 2(1/0) 1(0/0)
3(1/0) 2(1/0) 1(0/0)
3(0/1) 2(0/1) —
8(1/0) 7(1/0) 7(0/0)
4(0/1) 3(0/1) —
5(1/0) 3(1/0) 3(0/0)
5(1/0) 3(1/0) 3(0/0)
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