10.7 IMMEDIATE INSTRUCTION EXECUTION TIMES
Table 10-10 shows the number of clock cycles required for execution of the immediate
instructions, including completion of the operation and storing of the result. The number of
operand read and write cycles is shown in parentheses (r/w).
Table 10-10. Immediate Instruction Execution Times
Instruction
Size
ADDI
Byte, Word
"
Long
ADDQ
Byte, Word
"
Long
ANDI
Byte, Word
"
Long
CMPI
Byte, Word
"
Long
EORI
Byte, Word
"
Long
MOVEQ
Long
ORI
Byte, Word
"
Long
SUBI
Byte, Word
"
Long
SUBQ
Byte, Word
"
Long
1
Add 2(1/0) cycles to the (bd,An,Xi*SF) time for a memory indirect address.
MOTOROLA
(An)
Dn
An
(An)
+
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(0/
1(1/
1(1/
0)
0)
1)
1)
1(0/
1(0/
1(1/
1(1/
0)
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
0)
0)
1(0/
1(1/
1(1/
—
0)
0)
0)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
—
—
—
0)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(1/
1(1/
—
0)
1)
1)
1(0/
1(0/
1(1/
1(1/
0)
0)
1)
1)
1(0/
1(0/
1(1/
1(1/
0)
0)
1)
1)
M68060 USER'S MANUAL
Destination
–(An) (d16,An) (d8,An,Xi*SF) (bd,An,Xi*SF)
1(1/
2(1/1)
2(1/1)
1)
1(1/
2(1/1)
2(1/1)
1)
1(1/
1(1/1)
1(1/1)
1)
1(1/
1(1/1)
1(1/1)
1)
1(1/
2(1/1)
2(1/1)
1)
1(1/
2(1/1)
2(1/1)
1)
1(1/
2(1/0)
2(1/0)
0)
1(1/
2(1/0)
2(1/0)
0)
1(1/
2(1/1)
2(1/1)
1)
1(1/
2(1/1)
2(1/1)
1)
—
—
—
1(1/
2(1/1)
2(1/1)
1)
1(1/
2(1/1)
2(1/1)
1)
1(1/
2(1/1)
2(1/1)
1)
1(1/
2(1/1)
2(1/1)
1)
1(1/
1(1/1)
1(1/1)
1)
1(1/
1(1/1)
1(1/1)
1)
Instruction Execution Timing
1
(xxx).WL
3(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
1(1/1)
2(1/1)
1(1/1)
3(1/1)
2(1/1)
3(1/1)
2(1/1)
3(1/0)
2(1/0)
3(1/0)
2(1/0)
3(1/1)
2(1/1)
3(1/1)
2(1/1)
—
3(1/1)
2(1/1)
3(1/1)
2(1/1)
3(1/1)
2(1/1)
3(1/1)
2(1/1)
2(1/1)
1(1/1)
2(1/1)
1(1/1)
—
10-17