Burst-Inhibited Line Read Bus Cycle Timing - Motorola M68060 User Manual

BCLK
A31–A4
A1–A0
MISCELLANEOUS
ATTRIBUTES
R/W
SIZ1–SIZ0
BS3–BS0
CIOUT
CLA
A3–A2
TS
TIP
SAS
TA
TBI
D31–D0
NOTE: It is assumed that the acknowledge termination ignore state capability is disabled.
Figure 7-17. Burst-Inhibited Line Read Bus Cycle Timing
MOTOROLA
C1 C2 C3
LINE LONG
01 10
INHIBITED LONG-WORD
LINE READ READ
M68060 USER'S MANUAL
C4 C5 C6
LONG
11
LONG-WORD
READ
Bus Operation
C7 C8
LONG
00
LONG-WORD
READ
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