Data Cache Line State Diagrams - Motorola M68060 User Manual

Caches
Read misses and write misses to copyback pages cause the cache controller to read a new
cache line from memory into the cache. If available, an invalid line in the selected set is
updated with the tag and data from memory. The line state then changes from invalid to valid
by setting the V-bit for the line. If all lines in the set are already valid or dirty, the pseudo
round-robin replacement algorithm is used to select one of the four lines and replace the tag
and data contents of the line with the new line information. Before replacement, dirty lines
are temporarily buffered and later copied back to memory after the new line has been read
from memory. Snoops always check both the push buffer and the cache. Figure 5-7 illus-
trates the three possible states for a data cache line, with the possible transitions caused by
either the processor or snooped accesses. Transitions are labeled with a capital letter, indi-
cating the previous state, followed by a number indicating the specific case listed in Table
5-3.
CI5— CINV
CI6— CPUSH
WI3—CPU WRITE MISS
WI5—CINV
WI6—CPUSH
THROUGH
INVALID
5-18
CI1—CPU READ MISS
COPYBACK
INVALID
CV5—CINV
CV6—CPUSH
CV7—SNOOP HIT
CI3— CPU
WRITE MISS
CD5—CINV
CD6—CPUSH
CD7—SNOOP HIT
CD2— CPU READ HIT
CD3—CPU WRITE MISS
CD4—CPU WRITE HIT
COPYBACK CACHING MODE
WI1— CPU READ MISS
WRITE-
WV5— CINV
WV6— CPUSH
WV7—SNOOP HIT
WRITETHROUGH CACHING MODE
Figure 5-7. Data Cache Line State Diagrams
M68060 USER'S MANUAL
CV1—CPU READ MISS
CV2—CPU READ HIT
COPYBACK
CD1—CPU
READ MISS
CV3—CPU WRITE MISS
CV4—CPU WRITE HIT
COPYBACK
DIRTY
WV1—CPU READ MISS
WV2—CPU READ HIT
WV3—CPU WRITE MISS
WV4—CPU WRITE HIT
VALID
WRITE-
THROUGH
VALID
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