Data Bus Requirements For Read And Write Cycles - Motorola M68060 User Manual

Table 7-1. Data Bus Requirements for Read and Write Cycles
Transfer Size
SIZ1
Byte
Word
Long Word
Line
Table 7-1 lists the combinations of the SIZx, A1, and A0 signals, collectively called byte
enable signals, that are used for each of the four sections of the data bus. Alternatively, the
BSx signals may be used for byte selection. In Table 7-1, OP0–OP3 indicates the portion of
the requested operand that is read or written during that bus transfer. For line and long-word
transfers, all bytes are valid as listed and can correspond to portions of the requested oper-
and or to data required to fill the remainder of the cache line. The bytes labeled with a dash
are not required; they are ignored on read transfers and driven with undefined data on write
transfers. Not selecting these bytes prevents incorrect accesses in sensitive areas such as
I/O devices. Figure 7-8 illustrates a logic diagram for one method for generating byte select
signals from SIZx, A1, and A0 and the associated PAL equation. The logic shown in Figure
7-8 is equivalent to the internal logic used to generate the external byte select signals (BSx)
provided by the processor. Byte enable signals derived from the SIZx, A1, and A0 signals,
or alternatively, the external BSx signals, can be combined with the address or other
attributes signals to generate the decode logic of a system.
The MC68060 provides BSx so that it is unnecessary to use the SIZx, A1, and A0 signals to
generate byte selects using external logic. This aids in high-speed system design. Figure 7-
7, Figure 7-8, and Table 7-1 show the relationship between SIZx, A1, A0, and BSx.
A brief summary of the bus signal encoding for each access type is listed in Table 7-2. Addi-
tional information on the encoding for the MC68060 signals can be found in Section 2 Sig-
nal Description .
MOTOROLA
Signal Encoding
SIZ0 A1 A0
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 1 0
0 0 X X
1 1 X X
M68060 USER'S MANUAL
Active Data Bus Sections and Byte Enables
D31–D24 D23–D16
BS0 BS1
OP3 —
— OP3
— —
— —
OP2 OP3
— —
OP0 OP1
OP0 OP1
Bus Operation
D15–D8 D7–D0
BS2 BS3
— —
— —
OP3 —
— OP3
— —
OP2 OP3
OP2 OP3
OP2 OP3
7-7