Interrupt Recognition Examples - Motorola M68060 User Manual

with the MOVE to SR or RTE instruction). The level 6 interrupt request and mask level
example in Figure 8-3 is the same as for all interrupt levels except 7.
EXTERNAL
IPL2–IPL0
100 ($3)
IF 001 ($6)
IF 100 ($3)
IF 001 ($6)
IF STILL 001 ($6)
100 ($3)
IF 000 ($7)
IF 000 ($7)
IF 100 ($3)
IF
000 ($7)
IF STILL 000 ($7)
Note that a mask value of 6 and a mask value of 7 both inhibit request levels of 1–6 from
being recognized. In addition, neither masks an interrupt request level of 7. The only differ-
ence between mask values of 6 and 7 occurs when the interrupt request level is 7 and the
mask value is 7. If the mask value is lowered to 6, a second level 7 interrupt is recognized.
External circuitry can chain or otherwise merge signals from devices at each level, allowing
an unlimited number of devices to interrupt the processor. When several devices are con-
nected to the same interrupt level, each device should hold its interrupt priority level constant
until its corresponding interrupt acknowledge bus cycle ensures that all requests are pro-
cessed. Refer to Section 7 Bus Operation for details on the interrupt acknowledge cycle.
Figure 8-4 illustrates a flowchart for interrupt exception processing. When processing an
interrupt exception, the processor first makes an internal copy of the SR, sets the mode to
supervisor, suppresses tracing, and sets the processor interrupt mask level to the level of
the interrupt being serviced. The processor attempts to obtain a vector number from the
MOTOROLA
INTERRUPT PRIORITY
AND
AND STILL
AND STILL
AND RTE SO THAT
AND
AND
AND STILL
AND STILL
AND RTE SO THAT
Figure 8-3. Interrupt Recognition Examples
M68060 USER'S MANUAL
MASK (I2–I0) ACTION
101 ($5)
101 ($5) THEN LEVEL 6 INTERRUPT
110 ($6) THEN NO ACTION
110 ($6) THEN NO ACTION
101 ($5) THEN LEVEL 6 INTERRUPT
101 ($5)
101 ($5) THEN LEVEL 7 INTERRUPT
111 ($7) THEN NO ACTION
111 ($7) THEN NO ACTION
111 ($7) THEN LEVEL 7 INTERRUPT (TRANSITION)
101 ($5) THEN LEVEL 7 INTERRUPT (LEVEL COMPARISON)
Exception Processing
(INITIAL CONDITIONS)
(LEVEL COMPARISON)
(LEVEL COMPARISON)
(INITIAL CONDITIONS)
(TRANSITION)
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