Mc68060 Instruction And Data Caches; Instruction Cache Line Format; Data Cache Line Format - Motorola M68060 User Manual

Caches
EXECUTION UNIT
BRANCH
CACHE
pOEP
DECODE
FLOATING-
POINT
EA
UNIT
CALCULATE
OC
EA
EA
FETCH
FETCH
EX
FP
INT
EXECUTE
EXECUTE
DATA AVAILABLE
WRITE-BACK
Figure 5-1. MC68060 Instruction and Data Caches
bit for the line. Note that only the data cache supports dirty cache lines. Figure 5-2 illustrates
the instruction cache line format and Figure 5-3 illustrates the data cache line format.
WHERE:
TAG—21-BIT PHYSICAL ADDRESS TAG
V—VALID BIT FOR LINE
LWn—LONG WORD n (32-BIT) DATA ENTRY
TAG
WHERE:
TAG—21-BIT PHYSICAL ADDRESS TAG
V—VALID BIT FOR LINE
D—DIRTY BIT FOR LINE
LWn—LONG WORD n (32-BIT) DATA ENTRY
The cache stores an entire line, providing validity on a line-by-line basis. Only burst mode
accesses that successfully read four long words can be cached.
A cache line is always in one of three states: invalid, valid, or dirty. For invalid lines, the V-
bit is clear, causing the cache line to be ignored during lookups. Valid lines have their V-bit
set and D-bit cleared, the line contains valid data consistent with memory. Dirty cache lines
5-2
INSTRUCTION FETCH UNIT
IAG
IA
CALCULATE
IC
INSTRUCTION
FETCH
IED
EARLY
DECODE
IB
INSTRUCTION
BUFFER
sOEP
DS DS
DECODE
AG AG
EA
CALCULATE
OC EA OC
FETCH
EX INT EX
EXECUTE
INTEGER UNIT
DA
WB
OPERAND DATA BUS
TAG V LW3
Figure 5-2. Instruction Cache Line Format
V D LW3
Figure 5-3. Data Cache Line Format
M68060 USER'S MANUAL
INSTRUCTION INSTRUCTION
ATC CACHE
INSTRUCTION
CACHE
CONTROLLER
INSTRUCTION MEMORY UNIT
DATA
CACHE
CONTROLLER
DATA DATA
ATC CACHE
DATA MEMORY UNIT
LW2 LW1
LW2 LW1
ADDRESS
B
U
S
C
O
N
DATA
T
R
O
L
L
E
R
CONTROL
LW0
LW0
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