Mc68040 Bclk To Clken Relationship; Dram Timing Analysis - Motorola M68060 User Manual

Figure 11-10. MC68040 BCLK to CLKEN Relationship
11.2.8 Miscellaneous Pullup Resistors
Pullup CLA to prevent the A3 and A2 address lines from cycling on burst accesses. Pullup
TRA when MC68040 acknowledge termination mode is being used.
11.3 EXAMPLE DRAM ACCESS
When interfacing the MC68060 with dynamic random access memory (DRAM), it is neces-
sary to determine how many clocks per bus cycle will be needed for a line burst transfer.
The number of clocks per bus cycle is dependent upon the processor clock frequency and
the DRAM access times. In this example, the DRAM RAS access time, CAS access time,
RAS precharge time, and CAS precharge time are used to determine the number of clocks
per bus cycle of a DRAM access. Figure 11-11 shows two successive line burst transfers.
The CLA signal is used to cycle A3 and A2 a clock before the DRAM subsystem asserts TA.
CLK
TS
TA
CLA
A3–A2
DATA
(WRITE CYCLE)
DATA
(READ CYCLE)
RAS
CAS
DRAM ADDRESS
ROW
MOTOROLA
BCLK
CLK
CLKEN
W1 W2
W0
C0 C1 C2
Figure 11-11. DRAM Timing Analysis
M68060 USER'S MANUAL
W3 W0
C3
ROW
C0
Applications Information
W2
W1 W3
C3
C1 C2
11-15