10.8 Single-Operand Instruction Execution Times; Clear (Clr) Execution Times - Motorola M68060 User Manual

Instruction Execution Timing

10.8 SINGLE-OPERAND INSTRUCTION EXECUTION TIMES

Table 10-11 shows the number of clock cycles required for execution of the single-operand
instructions. The number of operand reads and write cycles is shown in parentheses (r/w).
Where indicated, the number of clock cycles and r/w cycles must be added to those required
for effective address calculation.
Table 10-11. Single-Operand Instruction Execution Times
Instruction
CAS
NBCD
NEG
NEGX
NOT
TAS
TST
1
Add (1 + effective address calculation time) cycles for all addressing modes
except Rn, (An), (An)+, –(An), and (d16,An).
2
Add the effective address calculation time to these instructions.
Execution times for the CLR instruction are given in Table 10-12. The number of operand
reads and writes is shown in parentheses (r/w).
A
Size Dn
n
Byte, Word 1(0/0) — 1(0/1)
Long 1(0/0) — 1(0/1)
1
Add 2(1/0) cycles to the (bd,An,Xi*SF) time for a memory indirect address.
10-18
Size
Byte, Word
"
Long
Byte
Byte, Word
" Long
Byte, Word
" Long
Byte, Word
" Long
Scc Byte -> False
" Byte -> True
Byte
Byte, Word
" Long
Table 10-12. Clear (CLR) Execution Times
(An) (An)+ –(An)
1(0/1) 1(0/1)
1(0/1) 1(0/1)
M68060 USER'S MANUAL
Register
1
—
1
—
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
(d16,An) (d8,An,Xi∗SF)
1(0/1) 1(0/1)
1(0/1) 1(0/1)
Memory
19(1/1)
19(1/1)
2
1(1/1)
2
1(1/1)
2
1(1/1)
2
1(1/1)
2
1(1/1)
2
1(1/1)
2
1(1/1)
2
1(1/1)
2
1(1/1)
2
17(1/1)
2
1(1/0)
2
1(1/0)
1
(bd,An,Xi∗SF) (xxx).WL
2(0/1) 1(0/1)
2(0/1) 1(0/1)
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