Line Read Access Bus Cycle Terminated With Tea Timing - Motorola M68060 User Manual

MISCELLANEOUS
ATTRIBUTES
Figure 7-38. Line Read Access Bus Cycle Terminated with TEA Timing
The processor retries any read or write bus cycles of a read-modify-write sequence sepa-
rately; LOCK remains asserted during the entire retry sequence. If the last bus cycle of a
locked access is retried, LOCKE remains asserted through the retry of the write bus cycle.
When in the MC68040 acknowledge termination mode, a retry termination on the initial long-
word transfer of a line access causes the processor to retry the bus cycle as illustrated in
Figure 7-40. However, the processor interprets a retry bus operation signaled during the
second, third, or fourth long-word transfer of a line burst bus cycle as a bus error and causes
the processor to abort the line transfer. However, when in the native-MC68060 acknowledge
termination mode, a retry termination signaled during the second, third, or fourth long-word
transfers of a line burst bus cycle are ignored.
MOTOROLA
C1 C2
BCLK
A31–A4
A1–A0
A3–A2 01
CLA
SIZ1–SIZ0
R/W
TS
TIP
SAS
TA
TEA
TBI
D31–D0
M68060 USER'S MANUAL
C3 C4
10 11
TEA ENDS BURST—
NO EXCEPTION
TAKEN
Bus Operation
7-49