Floating-Point Unit Block Diagram - Motorola M68060 User Manual

Floating-Point Unit
EXECUTION UNIT
BRANCH
CACHE
pOEP
DECODE
FLOATING-
POINT
EA
UNIT
CALCULATE
OC
EA
EA
FETCH
FETCH
EX
FP
INT
EXECUTE
EXECUTE
DATA AVAILABLE
WRITE-BACK
The MC68060 FPU has been optimized for the most frequently used instructions and data
types. The MC68060 fully conforms to the ANSI/IEEE 754–1985 Standard for Binary Float-
ing-Point Arithmetic . In addition, the MC68060 processor maintains compatibility with the
Motorola extended-precision architecture and is user object code compatible with the
MC68881/MC68882 floating-point coprocessors and the MC68040 microprocessor FPU.
With the inclusion of the M68060SP, the MC68060 provides MC68881/MC68882-compati-
ble software functions. Details on the M68060SP are provided in Appendix C MC68060
Software Package .
6.1 FLOATING-POINT USER PROGRAMMING MODEL
Figure 6-2 illustrates the floating-point portion of the user programming model. The following
paragraphs describe the FPU portion of the user programming model for the MC68060. The
model, which is identical to the programming model for the MC68881/MC68882 floating-
point coprocessors, consists of the following registers:
• Eight 80-Bit Floating-Point Data Registers (FP7–FP0)
• 16-Bit Floating-Point Control Register (FPCR)
• 32-Bit Floating-Point Status Register (FPSR)
• 32-Bit Floating-Point Instruction Address Register (FPIAR)
6-2
INSTRUCTION FETCH UNIT
IAG
IA
CALCULATE
IC
INSTRUCTION
FETCH
IED
EARLY
DECODE
IB
INSTRUCTION
BUFFER
sOEP
DS DS
DECODE
AG EA AG
CALCULATE
OC EA OC
FETCH
EX INT EX
EXECUTE
INTEGER UNIT
DA
WB
OPERAND DATA BUS
Figure 6-1. Floating-Point Unit Block Diagram
M68060 USER'S MANUAL
INSTRUCTION INSTRUCTION
ATC CACHE
INSTRUCTION
CACHE
CONTROLLER
INSTRUCTION MEMORY UNIT
DATA
CACHE
CONTROLLER
DATA DATA
CACHE
ATC
DATA MEMORY UNIT
ADDRESS
B
U
S
C
O
N
DATA
T
R
O
L
L
E
R
CONTROL
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