IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
Figure 9-7. General Arrangement of Bidirectional Pin Cells
Bit
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
9-10
TO NEXT CELL
OUTPUT
I/O.CTL
ENABLE
OUTPUT
O.PIN
DATA
INPUT
I.PIN
DATA
FROM
LAST CELL
Table 9-3. Boundary Scan Bit Definitions
Cell Type
O.Pin
I.Pin
O.Pin
I.Pin
IO.Ctl
O.Pin
I.Pin
O.Pin
I.Pin
O.Pin
I.Pin
O.Pin
I.Pin
IO.Ctl
O.Pin
I.Pin
O.Pin
I.Pin
O.Pin
I.Pin
O.Pin
I.Pin
IO.Ctl
O.Pin
I.Pin
O.Pin
I.Pin
O.Pin
I.Pin
O.Pin
I.Pin
IO.Ctl
M68060 USER'S MANUAL
EN
TO NEXT
PIN PAIR
Pin/Cell Name
A31
A31
A30
A30
A31–A28 ena
A29
A29
A28
A28
A27
A27
A26
A26
A27–A24 ena
A25
A25
A24
A24
A23
A23
A22
A22
A23–A20 ena
A21
A21
A20
A20
A19
A19
A18
A18
A19–A16 ena
I/O
PIN
Pin Type
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
—
MOTOROLA